参数资料
型号: TVP5150AEVM
厂商: Texas Instruments
文件页数: 52/74页
文件大小: 0K
描述: TVP5150AEVM
标准包装: 1
主要目的: 视频,视频解码器
已用 IC / 零件: TVP5150A
主要属性: NTSC/PAL 数字视频解码器
次要属性: 图形用户接口,I²C 接口
已供物品: 2 个板,线缆,CD,电源
配用: 296-23058-ND - EVAL MODULE FOR DM642
相关产品: TVP5150PBSR-ND - IC NTSC/PAL/SECAM DECODER 32TQFP
TVP5150APBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP
TVP5150AM1ZQCR-ND - IC VIDEO DECODER 8BIT 48BGA
TVP5150AM1PBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP
TVP5150AM1PBSG4-ND - IC VIDEO DECODER 8BIT 32TQFP
296-32781-ND - IC VIDEO DECODER 8BIT 32TQFP
296-32780-ND - IC VIDEO DECODER 8BIT 48BGA
296-27133-ND - IC VIDEO DECODER 8BIT 32TQFP
296-23026-6-ND - IC VIDEO DECODER 48-BGA
296-23025-6-ND - IC VIDEO DECODER 32-TQFP
更多...
246
2.20.56 Interrupt Enable Register A
Address
C1h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Lock interrupt
enable
Cycle complete
interrupt enable
Bus error
interrupt enable
Reserved
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with
a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded
with a 0 mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only
affects the interrupt on the external terminal, it does not affect the bits in interrupt status register A. A given condition
can set the appropriate bit in the status register and not cause an interrupt on the external terminal. To determine if
this device is driving the interrupt terminal either perform a logical AND of interrupt status register A with interrupt
enable register A, or check the state of the interrupt A bit in the interrupt configuration register at address C2h.
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled
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