参数资料
型号: TVP5150AEVM
厂商: Texas Instruments
文件页数: 16/74页
文件大小: 0K
描述: TVP5150AEVM
标准包装: 1
主要目的: 视频,视频解码器
已用 IC / 零件: TVP5150A
主要属性: NTSC/PAL 数字视频解码器
次要属性: 图形用户接口,I²C 接口
已供物品: 2 个板,线缆,CD,电源
配用: 296-23058-ND - EVAL MODULE FOR DM642
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213
2.17.2 RTC Mode
Figure 27 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO
clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long.
The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control.
RTC
M
S
B
16 CLK
L
S
B
21
0
128 CLK
22-Bit Fsc Frequency Control
Start
Bit
Reset
Bit
2 CLK
1 CLK
2 CLK
3 CLK
1 CLK
PAL
Switch
44 CLK
Figure 27. RTC Timing
2.18 Reset and Power Down
Terminals 8 (RESETB) and 28 (PDN) work together to put the TVP5150A decoder into one of the two modes.
Table 28 shows the configuration.
Table 28. Reset and Power Down Modes
PDN
RESETB
CONFIGURATION
0
Reserved (unknown state)
0
1
Powers down the decoder
1
0
Resets the decoder
1
Normal operation
2.19 Internal Control Registers
The TVP5150A decoder is initialized and controlled by a set of internal registers which set all device operating
parameters. Communication between the external controller and the TVP5150A decoder is through I2C. Table 29
shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined
registers must be written with 0s, unless otherwise noted. The detailed programming information of each register is
described in the following sections.
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