参数资料
型号: TVP5150AEVM
厂商: Texas Instruments
文件页数: 57/74页
文件大小: 0K
描述: TVP5150AEVM
标准包装: 1
主要目的: 视频,视频解码器
已用 IC / 零件: TVP5150A
主要属性: NTSC/PAL 数字视频解码器
次要属性: 图形用户接口,I²C 接口
已供物品: 2 个板,线缆,CD,电源
配用: 296-23058-ND - EVAL MODULE FOR DM642
相关产品: TVP5150PBSR-ND - IC NTSC/PAL/SECAM DECODER 32TQFP
TVP5150APBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP
TVP5150AM1ZQCR-ND - IC VIDEO DECODER 8BIT 48BGA
TVP5150AM1PBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP
TVP5150AM1PBSG4-ND - IC VIDEO DECODER 8BIT 32TQFP
296-32781-ND - IC VIDEO DECODER 8BIT 32TQFP
296-32780-ND - IC VIDEO DECODER 8BIT 48BGA
296-27133-ND - IC VIDEO DECODER 8BIT 32TQFP
296-23026-6-ND - IC VIDEO DECODER 48-BGA
296-23025-6-ND - IC VIDEO DECODER 32-TQFP
更多...
250
2.20.61 FIFO Interrupt Threshold Register
Address
C8h
Default
80h
7
6
5
4
3
2
1
0
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default
80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes.
2.20.62 FIFO Reset Register
Address
C9h
Default
00h
7
6
5
4
3
2
1
0
Any data
Writing any data to this register resets the FIFO and clears any data present.
2.20.63 Line Number Interrupt Register
Address
CAh
Default
00h
7
6
5
4
3
2
1
0
Field 1 enable
Field 2 enable
Line number
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This
interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable:
0 = Disabled (default)
1 = Enabled
Field 2 enable:
0 = Disabled (default)
1 = Enabled
Line number: (default 00h)
2.20.64 Pixel Alignment Registers
Address
CBh
CCh
Default
59h
03h
Address
7
6
5
4
3
2
1
0
CBh
Switch pixel [7:0]
CCh
Reserved
Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates
the program from one line standard to the next line standard; for example, the previous line of teletext to the next line
of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay
in the VDP, but early enough to allow the new values to be programmed before the current settings are required.
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