- 您现在的位置：买卖IC网 > PDF目录98307 > TVP7002PZPR (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP100 PDF资料下载
参数资料
| 型号： | TVP7002PZPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 21/57页 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZPR |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
SLES206B
– MAY 2007 – REVISED MAY 2011
H-PLL Phase Select
Subaddress
04h
Default (80h)
7
6
5
4
3
2
1
0
Phase Select [4:0]
Reserved
DIV2
Phase Select [4:0]: ADC sampling clock phase select. (1 LSB = 360/32 = 11.25
°). A host-based automatic phase control algorithm can be
used to control this setting to optimize graphics sampling phase.
00h = 0 degrees
10h = 180 degrees (default)
1Fh = 348.75 degrees
DIV2: DATACLK divide-by-2. H-PLL post divider. May be used with a 2x H-PLL feedback divider to improve jitter at low frequencies. When
used, only half of the Phase Select [4:0] settings are functional.
0 = DATACLK/1 (default)
1 = DATACLK/2
Clamp Start
Subaddress
05h
Default (32h)
7
6
5
4
3
2
1
0
Clamp Start [7:0]
Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected
this value has no meaning. Clamp Start must be correctly positioned for proper operation. See Table 13 for the recommended settings.
Clamp Width
Subaddress
06h
Default (20h)
7
6
5
4
3
2
1
0
Clamp Width [7:0]
Clamp Width [7:0]: Sets the width in pixels for the fine clamp. See also register Clamp Start (subaddress 05h).
Table 13. Recommended Fine Clamp Settings
VIDEO STANDARD
CLAMP START
CLAMP WIDTH
HDTV (tri-level)
50 (32h)
32 (20h)
SDTV (bi-level)
6 (06h)
16 (10h)
PC graphics
6 (06h)
16 (10h)
HSYNC Output Width
Subaddress
07h
Default (20h)
7
6
5
4
3
2
1
0
HSOUT Width [7:0]
HSOUT Width [7:0]: Sets the width in pixels for HSYNC output.
Blue Fine Gain
Subaddress
08h
Default (00h)
7
6
5
4
3
2
1
0
Blue Fine Gain [7:0]
Blue Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Blue channel (applied after the ADC). Offset binary value.
Blue Fine Gain = 1 + Blue Fine Gain [7:0]/256
Blue Fine Gain [7:0]
Blue Fine Gain
00h
1.0 (default)
80h
1.5
FFh
2.0
28
Copyright
2007–2011, Texas Instruments Incorporated
相关PDF资料 |
PDF描述 |
|---|---|
| TVP7002PZP | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| TWL1101PFB | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TWL1101PFBR | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TWL1102PBS | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
| TWL1102PBSR | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TVP9000MZDSR | 制造商:Texas Instruments 功能描述: |
| TVP9000ZDS | 制造商:Texas Instruments 功能描述: |
| TVP9000ZDSR | 制造商:Texas Instruments 功能描述: |
| TVP9001ZDS | 制造商:Texas Instruments 功能描述: |
| TVP9001ZDSR | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。