![](http://datasheet.mmic.net.cn/140000/TVP7002PZPR_datasheet_5023444/TVP7002PZPR_50.png)
SLES206B
– MAY 2007 – REVISED MAY 2011
F-bit Field 1 Start Line Offset
Subaddress
49h
Default (00h)
7
6
5
4
3
2
1
0
F-bit start 1 [7:0]
F-bit start 1 [7:0]: F-bit Field 1 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 1 until field 0 start line, it
only applies in interlaced mode. For a non-interlace mode, F-Bit is always set to 0.
NOTE: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT).
1st CSC Coefficient
Subaddress
4Ah
–4Bh
Default (16E3h)
Subaddress
7
6
5
4
3
2
1
0
4Ah
1st Coefficient [7:0]
4Bh
1st Coefficient [15:8]
1st Coefficient [15:0]: 16-bit G
’ coefficient MSB for Y
2nd CSC Coefficient
Subaddress
4Ch
–4Dh
Default (024Fh)
Subaddress
7
6
5
4
3
2
1
0
4Ch
2nd Coefficient [7:0]
4Dh
2nd Coefficient [15:8]
2nd Coefficient [15:0]: 16-bit B
’ coefficient MSB for Y
3rd CSC Coefficient
Subaddress
4Eh
–4Fh
Default (06CEh)
Subaddress
7
6
5
4
3
2
1
0
4Eh
3rd Coefficient [7:0]
4Fh
3rd Coefficient [15:8]
3rd Coefficient [15:0]: 16-bit R
’ coefficient MSB for Y
4th CSC Coefficient
Subaddress
50h
–51h
Default (F3ABh)
Subaddress
7
6
5
4
3
2
1
0
50h
4th Coefficient [7:0]
51h
4th Coefficient [15:8]
4th Coefficient [15:0]: 16-bit G
’ coefficient MSB for U
5th CSC Coefficient
Subaddress
52h
–53h
Default (1000h)
Subaddress
7
6
5
4
3
2
1
0
52h
5th Coefficient [7:0]
53h
5th Coefficient [15:8]
5th Coefficient [15:0]: 16-bit B
’ coefficient MSB for U
50
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2007–2011, Texas Instruments Incorporated