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参数资料
| 型号： | TVP7002PZPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 35/57页 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZPR |
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SLES206B
– MAY 2007 – REVISED MAY 2011
MISC Control 4
Subaddress
22h
Default (08h)
7
6
5
4
3
2
1
0
SP Reset
Yadj_delay [2:0]
MAC_EN
Coast Dis
VS Select
VS Bypass
SP Reset: Active-high reset for Sync Processing block. This bit may be used to manually reset the sync separator, sync accumulator,
activity and polarity detectors, and line and pixels counters.
0 = Normal operation (default)
1 = Sync processing reset
Yadj_delay [2:0]: Adjusts the phase delay of the luma output relative to the chroma output. Used to compensate for the chroma delay
associated with the 4:4:4 to 4:2:2 chroma sample conversion.
0h = Minimum delay (default)
7h = Maximum delay
MAC_EN: Toggling of the MAC_EN bit was required for TVP7000 and TVP7001 Macrovision support. This is no longer required with the
TVP7002.
0 = Macrovision stripper disabled (recommended setting for nominal HD and PC graphics inputs).
1 = Macrovision stripper enabled (default)
NOTE: When the Macrovsion stripper is enabled, ALC and Clamp pulse placement is affected by the Macrovision Stripper
Width setting. See Register 34h for details.
Coast Dis: Active-high internal coast signal disable for 5-wire PC graphics inputs. Has no effect when the external coast signal is selected.
See bit 5 of register 0Fh.
0 = Internal coast signal enabled (default)
1 = Internal coast signal disabled
VS Select: VSYNC select
0 = VSOUT is generated by the sync separator (default). When there is no sync separator activity, VSOUT
will be generated by the half line accumulator .
1 = VSOUT is generated by the half line accumulator
VS Bypass: VSYNC timing bypass
0 = Normal operation (default). VS is derived from the sync separator or half line accumulator based on VS select, and the
internal pixel/line counters. Register 35h can be used to adjust VSOUT alignment relative to HSOUT.
1 = Bypass VSYNC processing. VSOUT is derived directly from the sync separator. VSOUT delay varies with sync separator
threshold (register 11h). Register 35h has no effect.
Blue Digital ALC Output LSBs
Subaddress
23h
Read only
7
6
5
4
3
2
1
0
Blue ALC Out [7:0]
Blue ALC Out [7:0]: Eight LSBs of 10-bit filtered digital ALC output for Blue channel. The corresponding two MSBs are located at
subaddress 27h. With the internal ALC loop enabled, the ADC dynamic range can be maximized by adjusting the coarse offset settings
based on the ALC read back values. See registers 1Eh
–20h for analog coarse offset control. If large adjustments are made to the analog
coarse offset control, adequate time must be allowed for the ALC to converge prior to reading of this register. ALC delay requirements will
depend on the ALC NSV filter settings and the video input line rate. A delay of 30ms should be adequate for a 480i input with an NSV
setting of 1/64. ALC NSV filtering can be increased following final coarse offset adjsutment. See register 28h for more information on ALC
filter settings. Twos-complement value.
ALC Out[9:0] = ADC output
– 512
For bottom-level clamped inputs (YRGB):
Target ADC output blank level = 32 to avoid bottom level clipping at ADC
ALC Out[9:0] = 32
– 512 = –480 = 220h
Starting from positive offset, decrement YRGB coarse offset until ALC Out [9:0]
≤ 220h
For mid-level clamped inputs (PbPr):
Target ADC output blank level = 512
ALC Out[9:0] = 512
– 512 = 0
Starting from positive offset, decrement PbPr coarse offset until ALC Out [9:0]
≤ 0.
40
Copyright
2007–2011, Texas Instruments Incorporated
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