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参数资料
| 型号： | TVP7002PZPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 28/57页 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZPR |
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SLES206B
– MAY 2007 – REVISED MAY 2011
Output Formatter
Subaddress
15h
Default (04h)
7
6
5
4
3
2
1
0
Reserved
Output code range [1:0]
Reserved
Clamp REF
CbCr order
422/444
Sync En
Reserved [7]:
0 = Required (default)
Output code range [1:0]:
00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default)
01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019)
10 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)
11 = Reserved
Reserved [4]:
0 = Required (default)
Clamp REF: Selects which edge of HSYNC is used as the timing reference for the fine clamp pulse placement and also the ALC
placement.
0 = Clamp pulse placement referred to the trailing edge of HSYNC (default)
1 = Clamp pulse placement referred to the leading edge of HSYNC
CbCr order: This bit is only effective in the 4:2:2 output mode (i.e., bit 1 is set to 1).
0 = CbCr order
1 = CrCb order (default)
422/444: Active-high 4:4:4 to 4:2:2 decimation filter enable
0 = 30-bit 4:4:4 output format (default)
1 = 20-bit 4:2:2 output format
Notes:
1. Multiplexed CbCr data is output on BOUT [9:0] in the 20-bit 4:2:2 output format.
2. 10-bit 4:2:2 output format is not supported.
Sync En: Active-high embedded sync enable
0 = Embedded sync disabled (default)
1 = Embedded sync enabled
Notes:
1. Embedded syncs are not supported when the RGB coding range (0 to 1023) is selected.
2. Embedded syncs are not supported when the 30-bit 4:4:4 output format is selected.
3. Discrete syncs are always enabled except when outputs are placed in the high-impedance mode.
4. When enabled, embedded syncs are present in both the Y and C outputs.
MISC Control 1
Subaddress
16h
Default (11h)
7
6
5
4
3
2
1
0
Reserved
CbCr Align
Reserved
PLL PD
STRTB
CbCr Align: CbCr alignment
0 = Alternative operation
1 = Normal operation (default)
PLL PD: Active-high H-PLL power down
0 = Normal operation (default)
1 = H-PLL powered down
STRTB: Active-high H-PLL start-up circuit enable
0 = H-PLL start-up circuit disabled
1 = H-PLL start-up circuit enabled (default)
34
Copyright
2007–2011, Texas Instruments Incorporated
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