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参数资料
| 型号： | UDA1380TT |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封装： | 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32 |
| 文件页数： | 11/68页 |
| 文件大小： | 426K |
| 代理商： | UDA1380TT |
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2004 Apr 22
19
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8.11.1
ANALOG FRONT-END
Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is
done via separate L3-bus or I2C-bus bits.
handbook, full pagewidth
PGA
PGA_GAINCTRLR
PGA_GAINCTRLL
ADC
bitstream
right
ADC
SDC
bitstream
left
MGU534
PGA
VINL
VINR
VINM
SDC
LNA
SDC
PON_PGAL
PON_ADCL
PON_BIAS
FE
BIAS
VREF
PON_PGAR
PON_ADCR
PON_LNA
31
(27)
(29)
(31)
1
3
Fig.12 Analog front-end power-down.
Pin numbers for UDA1380HN in parentheses.
8.11.2
FSDAC POWER CONTROL
The FSDAC block has power-on pins: one of which shuts
down the DAC itself, but leaves the output still at VREF
voltage (which is half the power supply). This function is
set by the bit PON_DAC in the L3-bus or I2C-bus register.
A second L3-bus or I2C-bus bit shuts down the complete
bias circuit of the FSDAC, via bit PON_BIAS in the
L3-bus or I2C-bus register. This bit PON_BIAS acts the
same as given in Fig.12 for the analog front-end.
8.12
Plop prevention
Plops are ticks and other strange sounds that can occur
when a part of a device is powered-up or powered-down,
or when switching between modes is done.
Some ways to prevent plops from occurring are:
When the FSDAC or headphone driver must be
powered-down, first a digital mute is applied. After that
the FSDAC or headphone driver can be powered-down.
In case the FSDAC or headphone driver must be
powered-up, first the analog part is switched on, then the
digital part is demuted
When the ADC must be powered-down, a digital mute
sequence must be applied. When the digital output
signal is completely muted, the ADC can be
powered-down. In case the ADC must be powered-up,
first the analog part must be powered-up, then the digital
part must be demuted
When there is a change of, for example, clock divider
settings or clock source (selecting between SYSCLK
and WSPLL clock), then also digital mute for that block
(either decimator or interpolator) should be used.
Remark: All items mentioned in Section 8.12 are not
‘hard-wired’ implemented, but are to be followed by the
user as a guideline for plop prevention.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
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