- 您现在的位置：买卖IC网 > PDF目录199557 > UDA1380TT (NXP SEMICONDUCTORS) Stereo audio coder-decoder for MD, CD and MP3 PDF资料下载
参数资料
| 型号： | UDA1380TT |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封装： | 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32 |
| 文件页数： | 53/68页 |
| 文件大小： | 426K |
| 代理商： | UDA1380TT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
2004 Apr 22
57
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency (see Fig.16).
2. Tcy(s) is the cycle time of the sample frequency.
3. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
short as possible.
4. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1
64fs cycle.
5. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
6. After this period, the first clock pulse is generated.
7. To be suppressed by the input filter.
tstp(L3)
L3MODE stop time in data transfer
mode
190
ns
tsu(L3)DA
L3DATA set-up time in address and
data transfer mode
190
ns
th(L3)DA
L3DATA hold time in address and
data transfer mode
30
ns
td(L3)R
L3DATA delay time in data transfer
mode
0
50
ns
tdis(L3)R
L3DATA disable time for read data
0
50
ns
fSCL
SCL clock frequency
0
400
kHz
tLOW
SCL LOW time
1.3
μs
tHIGH
SCL HIGH time
0.6
μs
tr
rise time SDA and SCL
note 5
20 + 0.1Cb
300
ns
tf
fall time SDA and SCL
note 5
20 + 0.1Cb
300
ns
tHD;STA
hold time START condition
note 6
0.6
μs
tSU;STA
set-up time repeated START
0.6
μs
tSU;STO
set-up time STOP condition
0.6
μs
tBUF
bus free time between a STOP and
START condition
1.3
μs
tSU;DAT
data set-up time
100
ns
tHD;DAT
data hold time
0
μs
tSP
pulse width of spikes
note 7
0
50
ns
Cb
capacitive load for each bus line
400
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
相关PDF资料 |
PDF描述 |
|---|---|
| UEA1119C-HFD5-4F | 9 CONTACT(S), FEMALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SOLDER |
| UER100MF2XF | 100 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, SOCKET |
| UFM101 | SURFACE MOUNT GLASS PASSIVATED SUPER FAST SILICON RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere) |
| UFM102 | SURFACE MOUNT GLASS PASSIVATED SUPER FAST SILICON RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere) |
| UFM103 | SURFACE MOUNT GLASS PASSIVATED SUPER FAST SILICON RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
发布紧急采购，3分钟左右您将得到回复。