参数资料
型号: UDA1380TT
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO32
封装: 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32
文件页数: 37/68页
文件大小: 426K
代理商: UDA1380TT
2004 Apr 22
42
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.10 Mixer, silence detector and oversampling settings
Table 46 Register address 14H
Table 47 Description of register bits
BIT
15
14
13
12
11
10
9
8
Symbol
DA_POL_INV
SEL_NS
MIX_POS
MIX
Default
0
0000
BIT
7
6
5
4
3210
Symbol
SILENCE
SDET_ON
SD_VALUE1
SD_VALUE0
OS1
OS0
Default
0
0000
BIT
SYMBOL
DESCRIPTION
15
DA_POL_INV
DAC polarity control. A 1-bit value to control the signal polarity of the
DAC output signal. When this bit is logic 0: DAC output not inverted.
When this bit is logic 1: DAC output inverted. Default value 0.
14
SEL_NS
Noise shaper order select. A 1-bit value to select between the
3rd-order and the 5th-order noise shaper. When this bit is logic 0: select
3rd-order noise shaper. When this bit is logic 1: select 5th-order noise
shaper. Default value 0.
13
MIX_POS
Mixer signal control. A 2-bit value to select the digital mixer settings
inside the interpolation filter. Default value 0. By default the mixer is off,
12
MIX
11 to 8
default value 0000
7SILENCE
Silence mode. A 1-bit value to force the DAC output to silence. When
this bit is logic 0: no overruling. The setting of the FSDAC silence switch
depends on the status of the digital silence detector circuit and the
master_mute status. When this bit is logic 1: overruling. The FSDAC
silence switch is activated, independent of the status of the digital
silence detector circuit or the master_mute status. Default value 0.
6SDET_ON
Silence detector enable. A 1-bit value to enable the digital silence
detector. When this bit is logic 0: silence detection circuit disabled.
When this bit is logic 1: silence detection circuit enabled. Default
value 0.
5 and 4
SD_VALUE[1:0]
Silence detector settings. A 2-bit value to program the silence
detector, the number of ‘ZERO’ samples counted before the silence
detector signals whether there has been digital silence. Default
value 00, see Table 49.
3 and 2
default value 00
1 and 0
OS[1:0]
Oversampling input settings. A 2-bit value to select the oversampling
input mode. Default value 00, see Table 50.
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