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参数资料
| 型号： | UDA1380TT |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封装： | 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32 |
| 文件页数： | 3/68页 |
| 文件大小： | 426K |
| 代理商： | UDA1380TT |
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2004 Apr 22
11
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8
FUNCTIONAL DESCRIPTION
8.1
Clock modes
There are two clock systems:
A SYSCLK signal, coming from the system
A WSPLL which generates the internal clocks from the
incoming WSI signal.
The system frequency applied to pin SYSCLK is
selectable. The options are 256fs, 384fs, 512fs and 768fs.
The system clock must be locked in frequency to the digital
interface signals.
Remark: Since there is neither a fixed reference clock
available in the IC itself, nor a fixed clock available in the
system the IC is in, there is no auto sample rate conversion
detection circuitry.
The system can run in several modes, using the two clock
systems:
Both the DAC and the ADC part can run at the applied
SYSCLK input. In this case the WSPLL is
powered-down
The ADC can run at the SYSCLK input, and at the same
time the DAC part can run (at a different frequency) at
the clock re-generated from the WSI signal
The ADC and the DAC can both run at the clock
regenerated from the WSI signal.
8.1.1
WSPLL REQUIREMENTS
The WSPLL is meant to lock onto the WSI input signal, and
regenerates 256fs and 128fs signals for the FSDAC and
the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from
75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as
that the user must set the input range of the WSI input
signal.
In case the SYSCLK is used for clocking the complete
system (decimator including interpolator) the WSPLL must
be powered-down with bit ADC_CLK via the L3-bus
or I2C-bus.
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1
and PLL0 bits in the L3-bus or I2C-bus register.
handbook, halfpage
VCO
WSI
DIV1
128fs
(digital parts)
256fs
(ADC and FSDAC)
PRE1
MGU527
Fig.4 WSPLL set-up.
Table 1
WSPLL divider settings
WORD SELECT
FREQUENCY (kHz)
SEL_LOOP_DIV[1:0]
PRE1
DIV1
VCO FREQUENCY
(MHz)
6.25 to 12.5
00
8
1536
76 to 153
12.5 to 25
01
4
1536
25 to 50
10
2
1536
50 to 100
11
2
768
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相关代理商/技术参数 |
参数描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
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