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参数资料
| 型号： | UDA1380TT |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封装： | 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32 |
| 文件页数： | 24/68页 |
| 文件大小： | 426K |
| 代理商： | UDA1380TT |
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2004 Apr 22
30
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.1
Evaluation modes and clock settings
Table 17 Register address 00H
Table 18 Description of register bits
BIT
151413
12
11
10
9
8
Symbol
EV2
EV1
EV0
EN_ADC
EN_DEC
EN_DAC
EN_INT
Default
0
000101
BIT
7
6
543210
Symbol
ADC_CLK
DAC_CLK
sys_div1
sys_div0
PLL1
PLL0
Default
0
000010
BIT
SYMBOL
DESCRIPTION
15 to 13
EV[2:0]
Evaluation bits. Bits EV2, EV1 and EV0 are special control bits for
manufacturer’s evaluation and must always be kept at their default values for
normal operation of UDA1380; default value 000.
12
default value 0
11
EN_ADC
ADC clock enable. A 1-bit value to enable the system clock (from SYSCLK
input) to the analog part of the ADC. See Fig.5 for more detailed information.
When this bit is logic 0: clock to ADC disabled and when this bit is logic 1:
clock to ADC running. Default value 0.
10
EN_DEC
Decimator clock enable. A 1-bit value to enable the 128fs clock to the
decimator, the 128fs part of the I2S-bus output block and the clock to the ADC
this bit is logic 0: clock to the decimator disabled. When this bit is logic 1:
clock to the decimator running. Default value 1.
9
EN_DAC
FSDAC clock enable. A 1-bit value to enable the 256fs clock to the analog
part of the FSDAC. See Fig.5 for more detailed information. When this bit is
logic 0: clock to FSDAC disabled. When this bit is logic 1: clock to the FSDAC
running. Default value 0.
8EN_INT
Interpolator clock enable. A 1-bit value to enable the 128fs clock to the
interpolator, the 128fs part of the I2S-bus input block and the interpolator
information. When this bit is logic 0: clock to the interpolator disabled. When
this bit is logic 1: clock to the interpolator running. Default value 1.
7and 6
default value 00
5
ADC_CLK
ADC clock select. A 1-bit value to select the 128fs clock and the clock of the
analog part for the decimator and the ADC. This can either be the clock
derived from the SYSCLK input or from the WSPLL. When this bit is logic 0:
SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
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