参数资料
型号: UDA1380TT
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO32
封装: 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32
文件页数: 39/68页
文件大小: 426K
代理商: UDA1380TT
2004 Apr 22
44
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 53 ADC volume control setting bits
11.12 PGA settings and mute
Table 54 Register address 21H
Table 55 Description of register bits
ML_DEC7
MR_DEC7
ML_DEC6
MR_DEC6
ML_DEC5
MR_DEC5
ML_DEC4
MR_DEC4
ML_DEC3
MR_DEC3
ML_DEC2
MR_DEC2
ML_DEC1
MR_DEC1
ML_DEC0
MR_DEC0
GAIN (dB)
001
1000
0
24
001
0111
1
23.5
001
0111
0
23
::
:::::
:
000
0001
0
1
000
0000
1
0.5
000
0000
0
0 (default)
111
1111
1
0.5
::
:::::
:
100
0010
0
62
100
0001
1
62.5
100
0001
0
63
100
0000
1
63.5
100
0000
0
BIT
15
141312
11
10
9
8
Symbol
MT_ADC
PGA_GAIN
CTRLR3
PGA_GAIN
CTRLR2
PGA_GAIN
CTRLR1
PGA_GAIN
CTRLR0
Default
1
0
00
BIT
7
6
5
4
32
10
Symbol
PGA_GAIN
CTRLL3
PGA_GAIN
CTRLL2
PGA_GAIN
CTRLL1
PGA_GAIN
CTRLL0
Default
0
00
BIT
SYMBOL
DESCRIPTION
15
MT_ADC
Decimator mute. A 1-bit value to enable the digital linear mute. When this bit is
logic 0: no muting. When this bit is logic 1: muting. Default value 1.
14 to 12
default value 000
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