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| 型号： | USB-EA-CONVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/68页 |
| 文件大小： | 0K |
| 描述： | SUPPORT BOARD ADUC8XX |
| 标准包装： | 1 |
| 类型： | 仿真器 |
| 适用于相关产品： | ADuC8xx |
| 所含物品： | 模块 |
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REV. B
ADuC824
–24–
SPECIAL FUNCTION REGISTERS
All registers, except the program counter and the four general-
purpose register banks, reside in the SFR area. The SFR registers
include control, configuration, and data registers that provide
an interface between the CPU and all on-chip peripherals.
SPICON
F8H
04H
RESERVED RESERVED
RESERVED
NOT USED
RESERVED
RESERVED RESERVED
RESERVED
RESERVED RESERVED
RESERVED
NOT USED
RESERVED
RESERVED RESERVED
RESERVED
NOT USED
DACL
FBH
00H
DACH
FCH
00H
DACCON
FDH
00H
B
F0H
00H
I2CCON
E8H
00H
ACC
E0H
00H
ADCSTAT
D8H
00H
PSW
D0H
00H
T2CON
00H
WDCON
C0H
10H
IP
B8H
00H
P3
B0H
FFH
IE
A8H
00H
P2
A0H
FFH
SCON
98H
00H
P1
90H
FFH
TCON
88H
00H
P0
80H
FFH
E9H
55H
OF0L*
E1H
00H
ADC0L
D9H
00H
ADCMODE
D1H
00H
ECON
B9H
00H
IEIP2
A9H
A0H
TIMECON
A1H
00H
SBUF
99H
00H
TMOD
89H
00H
SP
81H
07H
NOT USED
EAH
55H
OF0M*
E2H
00H
ADC0M
DAH
00H
ADC0CON
D2H
07H
RCAP2L
CAH
00H
CHIPID
C2H
06H
HTHSEC
A2H
00H
I2CDAT
9AH
00H
TL0
8AH
00H
DPL
82H
00H
EBH
53H
OF0H*
E3H
80H
ADC0H
DBH
00H
ADC1CON
D3H
00H
RCAP2H
CBH
00H
SEC
A3H
00H
TL1
8BH
00H
DPH
83H
00H
RESERVED
I2CDAT
00H
9AH
GN1L*
ECH
9AH
OF1L*
E4H
00H
ADC1L
DCH
00H
SF
D4H
45H
TL2
CCH
00H
EDATA1
BCH
00H
MIN
A4H
00H
TH0
8CH
00H
DPP
84H
00H
RESERVED
GN1H*
EDH
59H
OF1H*
E5H
80H
ADC1H
DDH
00H
ICON
D5H
00H
TH2
CDH
00H
EDATA2
BDH
00H
HOUR
A5H
00H
TH1
8DH
00H
RESERVED
EADRL
C6H
00H
EDATA3
BEH
00H
INTVAL
A6H
00H
SPIDAT
F7H
00H
PSMCON
DFH
DEH
PLLCON
D7H
03H
EDATA4
BFH
00H
PCON
87H
00H
GN0L*
GN0M*
GN0H*
C8H
NOT USED
ISPI
FFH
0
WCOL
FEH
0
SPE
FDH
0
SPIM
FCH
0
CPOL
FBH
0
CPHA
FAH
SPR1
F9H
0
SPR0
F8H
0
BITS
F7H
0
F6H
0
F5H
0
F4H
0
F3H
0
F2H
F1H
0 F0H
0
BITS
MDO
EFH
0
MDE
EEH
0
MCO
EDH
0
MDI
ECH
0
I2CM
EBH
0
I2CRS
EAH
I2CTX
E9H
0
I2CI
E8H
0
BITS
E7H
0
E6H
0
E5H
0
E4H
0
E3H
0
E2H
E1H
0 E0H
0
BITS
RDY0
DFH
0
RDY1
DEH
0
CAL
DDH
0
NOXREF
DCH
0
ERR0
DBH
0
ERR1
DAH
D9H
0 D8H
0
BITS
CY
D7H
0
AC
D6H
0
F0
D5H
0
RSI
D4H
0
RS0
D3H
0
OV
D2H
FI
D1H
0
P
D0H
0
BITS
TF2
CFH
0
EXF2
CEH
0
RCLK
CDH
0
TCLK
CCH
0
EXEN2
CBH
0
TR2
CAH
CNT2
C9H
0
CAP2
C8H
0
BITS
PRE2
C7H
0
PRE1
C6H
0
PRE0
C5H
0
C4H
1
WDIR
C3H
0
WDS
C2H
WDE
C1H
0
WDWR
C0H
0
BITS
BFH
0
PADC
BEH
0
PT2
BDH
0
PS
BCH
0
PT1
BBH
0
PX1
BAH
PT0
B9H
0
PX0
B8H
0
BITS
RD
B7H
1
WR
B6H
1
T1
B5H
1
T0
B4H
1
INT1
B3H
1
INT0
B2H
TXD
B1H
1
RXD
B0H
1
BITS
EA
AFH
EADC
AEH
ET2
ADH
ES
ACH
0
ET1
ABH
0
EX1
AAH
ET0
A9H
0
EX0
A8H
0
BITS
A7H
A6H
A5H
1
A4H
1
A3H
1
A2H
A1H
1 A0H
1
BITS
SM0
9FH
0
SM1
9EH
0
SM2
9DH
0
REN
9CH
0
TB8
9BH
0
RB8
9AH
T1
99H
0
R1
98H
0
BITS
97H
1
96H
1
95H
1
94H
1
93H
1
92H
T2EX
91H
1
T2
90H
1
BITS
TF1
8FH
0
TR1
8EH
0
TF0
8DH
0
TR0
8CH
0
IE1
8BH
0
IT1
8AH
IE0
89H
0
IT0
88H
0
BITS
87H
1
86H
1
85H
1
84H
1
83H
1
82H
81H
1 80H
1
BITS
1
0
1
0
1
0
PRE3
00
0
11
*CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.
IE0
89H
0
IT0
88H
0
TCON
88H
00H
BIT MNEMONIC
BIT BIT ADDRESS
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
THESE BITS ARE CONTAINED IN THIS BYTE.
DEFAULT BIT VALUE
SFR MAP KEY:
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE.
Figure 17. Special Function Register Locations and Reset Values
Figure 17 shows a full SFR memory map and SFR contents on
RESET NOT USED indicates unoccupied SFR locations. Unoc-
cupied locations in the SFR address space are not implemented;
i.e., no register exists at this location. If an unoccupied location
is read, an unspecified value is returned. SFR locations reserved
for future use are shaded (RESERVED) and should not be
accessed by user software.
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