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参数资料
| 型号： | V58C2128404SBLT6I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封装： | 0.400 X 0.875 INCH, PLASTIC, MS-024FC, TSOP2-66 |
| 文件页数： | 29/60页 |
| 文件大小： | 915K |
| 代理商： | V58C2128404SBLT6I |
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35
ProMOS TECHNOLOGIES
V58C2128(804/404/164)SB*I
V58C2128(804/404/164)SB*I Rev. 1.3 March 2006
IDD Max Specifications and Conditions
(-40°C < TA < +85°C, VDDQ=2.5V+ 0.2V, VDD=2.5 +0.2V, for DDR400 device VDDQ=2.6V+ 0.1V, VDD=2.6 +0.1V)
Conditions
Version
Symbol
-5
-6
Unit
Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=166Mhz for DDR333 and
tCK=200Mhz for DDR400; DQ,DM and DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
IDD0
115
100
mA
Operating current - One bank operation; One bank open, BL=4
IDD1
135
115
mA
Precharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max);
tCK=166Mhz for DDR333 and tCK=200Mhz for DDR400; Vin = Vref for DQ,DQS and DM
IDD2P
20
15
mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=166Mhz
for DDR333 and tCK=200Mhz for DDR400; Address and other control inputs changing once per clock
cycle; Vin = Vref for DQ,DQS and DM
IDD2F
52
45
mA
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 166Mhz
for DDR333 and tCK=200Mhz for DDR400; Address and other control inputs stable with keeping >=
VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
IDD2Q
50
44
mA
Active power - down standby current; one bank active; power-down mode; CKE=< VIL (max); tCK =
166Mhz for DDR333 and tCK=200Mhz for DDR400; Vin = Vref for DQ,DQS and DM
IDD3P
25
20
mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge;
tRC=tRASmax; tCK = 166Mhz for DDR333 and tCK=200Mhz for DDR400; DQ, DQS and DM inputs
changing twice per clock cycle; address and other control inputs changing once per clock cycle
IDD3N
50
40
mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address
and control inputs changing once per clock cycle; tCK = 166Mhz for DDR333 and tCK=200Mhz for
DDR400; 50% of data changing at every burst; lout = 0 m A
IDD4R
135
115
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and
control inputs changing once per clock cycle; tCK = 166Mhz for DDR333 and tCK=200Mhz for DDR400;
DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst
IDD4W
155
135
mA
Auto refresh current; tRC = tRFC(min) -12*tCK for DDR333 at 166Mhz, 14*tCK for DDR333B; distrib-
uted refresh
IDD5
210
200
mA
Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 166Mhz for DDR333 and
tCK=200Mhz for DDR400.
Self refresh current; (Low Power)
IDD6
(normal)
1.0
mA
(L)
0.8
mA
Operating current - Four bank operation; Four bank interleaving with BL=4
IDD7
355
325
mA
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