参数资料
型号: V58C2128404SBLT6I
厂商: PROMOS TECHNOLOGIES INC
元件分类: DRAM
英文描述: 32M X 4 DDR DRAM, 0.7 ns, PDSO66
封装: 0.400 X 0.875 INCH, PLASTIC, MS-024FC, TSOP2-66
文件页数: 31/60页
文件大小: 915K
代理商: V58C2128404SBLT6I
37
ProMOS TECHNOLOGIES
V58C2128(804/404/164)SB*I
V58C2128(804/404/164)SB*I Rev. 1.3 March 2006
Address and control input hold time
(fast slew rate)
tIH
F
0.60
0.75
ns
14
Address and control input setup time
(fast slew rate)
tIS
F
0.60
0.75
ns
14
Address and control input hold time
(slow slew rate)
tIH
S
0.70
0.80
ns
14
Address and control input setup time
(slow slew rate)
tIS
S
0.70
0.80
ns
14
LOAD MODE REGISTER command cycle time
tMRD
2
tCK
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tQH
tHP
-tQHS
tHP
-tQHS
ns
25, 26
Data hold skew factor
tQHS
0.50
0.55
ns
ACTIVE to PRECHARGE command
tRAS
40
70,000
42
120,000
ns
35
ACTIVE to READ with Auto precharge
command
tRAP
15
18
ns
46
ACTIVE to ACTIVE/AUTO REFRESH
command period
tRC
60
ns
AUTO REFRESH command period
tRFC
70
72
ns
50
ACTIVE to READ or WRITE delay
tRCD
15
18
ns
PRECHARGE command period
tRP
15
18
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
42
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
20, 21
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
19
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
2
tCK
Data valid output window
na
tQH - tDQSQ
ns
25
Average periodic refresh interval
tREFI
15.6
us
Terminating voltage delay to VDD
tVTD
0
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
相关PDF资料
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