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参数资料
| 型号： | V58C2256404SHUR5 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, PBGA60 |
| 封装： | ROHS COMPLIANT, MO-233, FBGA-60 |
| 文件页数： | 21/60页 |
| 文件大小： | 1125K |
| 代理商： | V58C2256404SHUR5 |
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V58C2256(804/404/164)SH Rev. 1.1 July 2010
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
Note
H
X
LLLL
OP code
1,2
H
X
LLLL
1,2
Device Deselect
HX
H
XXX
X1
No
L
HHH
Bank Active
H
X
L
H
RA
V
1
Read
H
X
LHLH
CA
L
V
1
Read with Autoprecharge
H1,3
Write
HX
L
H
L
CA
L
V
1
Write with Autoprecharge
H1,4
Precharge All Banks
HX
L
H
L
X
HX
1,5
Precharge selected Bank
LV
1
Read Burst Stop
H
X
L
H
L
X
1
Auto
H
LLL
H
X
1
Self Refresh
Entry
H
L
LLL
H
X
1
Exit
L
H
XXX
1
LH
H
Precharge Power
Down Mode
Entry
H
L
H
XXX
X
1
LH
H
1
Exit
L
H
XXX
1
LH
H
1
Active Power
Down Mode
Entry
H
L
H
XXX
X
1
L
VVV
1
Exit
L
H
X
1
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
OP code
Refresh
Operation
Mode Register Set
Extended Mode Register Set
,6
6. This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto
precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write
data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write
data must be avoided).
DDR SDRAM SIMPLIFIED COMMAND TRUTH TABLE
相关PDF资料 |
PDF描述 |
|---|---|
| V58C2256804SHLI4I | 32M X 8 DDR DRAM, PDSO66 |
| V58C2256804SHLJ6E | 32M X 8 DDR DRAM, PBGA60 |
| V58C2256804SHLS6I | 32M X 8 DDR DRAM, PBGA60 |
| V58C2256804SHLT6E | 32M X 8 DDR DRAM, PDSO66 |
| V58C2256804SHUD6E | 32M X 8 DDR DRAM, PDSO66 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V58C2256804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804SAT-5 | 制造商:Mosel Vitelic Corporation 功能描述:SDRAM, DDR, 32M x 8, 66 Pin, Plastic, TSSOP |
| V58C265164S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
| V58C265804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
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