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参数资料
| 型号： | V58C2256404SHUR5 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, PBGA60 |
| 封装： | ROHS COMPLIANT, MO-233, FBGA-60 |
| 文件页数： | 26/60页 |
| 文件大小： | 1125K |
| 代理商： | V58C2256404SHUR5 |
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32
V58C2256(804/404/164)SH Rev. 1.1 July 2010
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
NOTE: (continued)
Read with Auto Precharge Enabled: See following text
Write with Auto Precharge Enabled: See following text
3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken
into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge
period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the
earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto
Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was
disabled. The access period starts with registration of the command and ends where the precharge period
(or tRP) begins.
During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled
states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; All
other related limitations apply (e.g. contention between READ data and WRITE data must be avoided).
3b. This device supports “concurrent auto precharge”. This feature allows a read with auto precharge enabled, or
a write with auto precharge enabled, to be followed by any command to the other banks, as long as that com-
mand does not interrrupt the read or write data transfer, and all other related limitations apply (e.g. contention
between READ data and WRITE data must be avoided.)
3c. The minimum delay from a read or write command with auto precharge enable, to a command to a different
bank, is sumarized below, for both cases of “concurrent auto precharge,” supported or not:
4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the
current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of data output.
From
Command
To Command
(different bank)
Minimum Delay without
Concurrent Auto
Precharge Support
Minimum Delay with
Concurrent Auto
Precharge Support
Units
Write w/AP
Read or
Read w/AP
1+(BL/2)+(tWR/tCK)
(rounded up)
1+(BL/2)+tWTR
tCK
Write or
Write w/AP
1+(BL/2)+(tWR/tCK)
(rounded up)
BL/2
tCK
Precharge or
Activate
1tCK
Read w/AP
Read or
Read w/AP
BL/2
tCK
Write or
Write w/AP
CL(rounded up) + (BL/2)
tCK
Precharge or
Activate
1tCK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| V58C2256804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804SAT-5 | 制造商:Mosel Vitelic Corporation 功能描述:SDRAM, DDR, 32M x 8, 66 Pin, Plastic, TSSOP |
| V58C265164S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
| V58C265804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
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