参数资料
型号: W25Q80BVSFIG
厂商: WINBOND ELECTRONICS CORP
元件分类: PROM
英文描述: 1M X 8 SPI BUS SERIAL EEPROM, PDSO16
封装: 0.300 INCH, GREEN, PLASTIC, SOIC-16
文件页数: 31/72页
文件大小: 1878K
代理商: W25Q80BVSFIG
W25Q80BV
Publication Release Date: March 26, 2009
- 37 -
Preliminary - Revision A
10.2.18 Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page.
Certain applications can benefit from this feature and improve the overall system code execution
performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in figure 17. Wrap bit W7 and the lower nibble W3-0 are not used.
W4 = 0
W4 =1 (default)
W6, W5
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0
Yes
8-byte
No
N/A
0
1
Yes
16-byte
No
N/A
1
0
Yes
32-byte
No
N/A
1
Yes
64-byte
No
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any
page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with
Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case
of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap
instruction to reset W4 = 1 prior to any normal Read instructions since W25Q80BV does not have a
hardware Reset Pin.
/CS
CLK
/CS
CLK
Figure 17. Set Burst with Wrap Instruction Sequence
01
23
4
5
67
89
10
11
12
13
14
15
Mode 3
Mode 0
IO0
IO1
IO2
IO3
Instruction (77h)
don’t care don’t care don’t care
wrap bit
X
w6
w5
w4
X
01
23
4
5
67
89
10
11
12
13
14
15
Mode 3
Mode 0
Instruction (77h)
IO0
IO1
IO2
IO3
don’t care don’t care don’t care
wrap bit
X
w6
w5
w4
X
w6
w5
w4
X
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