参数资料
型号: W25X20-VSNI
厂商: WINBOND ELECTRONICS CORP
元件分类: PROM
英文描述: 2M X 1 FLASH 2.7V PROM, PDSO8
封装: 0.150 INCH, PLASTIC, SOIC-8
文件页数: 10/42页
文件大小: 1198K
代理商: W25X20-VSNI
W25X10, W25X20, W25X40 AND W25X80
- 18 -
9.2.6
Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable
instruction must previously have been executed for the device to accept the Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by
driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as
illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this data
sheet.
Only non-volatile Status Register bits SRP, TB, BP2, BP1 and BP0 (bits 7, 5, 4, 3 and 2) can be
written to. All other Status Register bit locations are read-only and will not be affected by the Write
Status Register instruction.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed
Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While
the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed
to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a
0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0) to be set
for protecting all, a portion, or none of the memory from erase and program instructions. Protected
areas become read-only (see Status Register Memory Protection table). The Write Status Register
instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction
with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0
state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a
1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is
high the Write Status Register instruction is allowed.
Figure 7. Write Status Register Instruction Sequence Diagram
相关PDF资料
PDF描述
WS512K32-100G4Q 2M X 8 MULTI DEVICE SRAM MODULE, 100 ns, CQFP68
WF8M32-100G4DM5 8M X 32 FLASH 5V PROM MODULE, 100 ns, CQFP68
WF8M32-120G4DI5 8M X 32 FLASH 5V PROM MODULE, 120 ns, CQFP68
WMS512K8B-15CIEA 512K X 8 STANDARD SRAM, 15 ns, CDIP32
WMS512K8B-17DEMEA 512K X 8 STANDARD SRAM, 20 ns, CDSO32
相关代理商/技术参数
参数描述
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