参数资料
型号: W25X20-VSNI
厂商: WINBOND ELECTRONICS CORP
元件分类: PROM
英文描述: 2M X 1 FLASH 2.7V PROM, PDSO8
封装: 0.150 INCH, PLASTIC, SOIC-8
文件页数: 16/42页
文件大小: 1198K
代理商: W25X20-VSNI
W25X10, W25X20, W25X40 AND W25X80
Publication Release Date: February 13, 2006
- 23 -
Revision E
9.2.11 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure
2). The Sector Erase instruction sequence is shown in figure 12.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector
Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Sector Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector
Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB,
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
Figure 12. Sector Erase Instruction Sequence Diagram
相关PDF资料
PDF描述
WS512K32-100G4Q 2M X 8 MULTI DEVICE SRAM MODULE, 100 ns, CQFP68
WF8M32-100G4DM5 8M X 32 FLASH 5V PROM MODULE, 100 ns, CQFP68
WF8M32-120G4DI5 8M X 32 FLASH 5V PROM MODULE, 120 ns, CQFP68
WMS512K8B-15CIEA 512K X 8 STANDARD SRAM, 15 ns, CDIP32
WMS512K8B-17DEMEA 512K X 8 STANDARD SRAM, 20 ns, CDSO32
相关代理商/技术参数
参数描述
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