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参数资料
| 型号： | W28J800BT90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 512K X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封装： | 12 X 20 MM, TSOP-48 |
| 文件页数： | 2/49页 |
| 文件大小： | 1527K |
| 代理商： | W28J800BT90L |
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W28J800B/T
- 10 -
8. BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Read
Information can be read from any block, identifier codes or status register independent of the VPP
voltage. #RESET can be at VIH.
The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode, the
device automatically resets to read array mode. Six control pins dictate the data flow in and out of the
component: #CE, #OE, #BYTE, #WE, #RESET and #WP. #CE and #OE must be driven active to
obtain data at the outputs. #CE is the device selection control, and when active enables the selected
memory device. #OE is the data output (DQ0
DQ15) control and when active drives the selected
memory data onto the I/O bus. #BYTE is the device I/O interface mode control. #WE must be at VIH,
#RESET must be at VIH, and #BYTE and #WP must be at VIL or VIH. Figure 16, 17 illustrates read
cycle.
Output Disable
With #OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0
DQ15) are
placed in a high-impedance state.
Standby
Setting #CE to a logic-high level (VIH) deselects the device and places it in standby mode, which
substantially reduces device power consumption. DQ0
DQ15 outputs are placed in a high
impedance state independent of #OE. If deselected during block erase, full chip erase, word/byte write
or lock-bit configuration, the device continues functioning, and it continues to consume active power
until the operation is completed.
Reset
Setting #RESET to VIL initiates the reset mode.
In read modes, setting #RESET at VIL deselects the memory, places output drivers in a high-
impedance state and turns off all internal circuits. #RESET must be held low for a minimum of 100 nS.
A delay (tPHQV) is required after return from reset until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The CUI is reset to read array mode status register
is set to 80H.
During block erase, full chip erase, word/byte write or lock-bit configuration modes, #RESET at VIL will
abort the operation. RY/#BY remains low until the reset operation is complete. Memory contents at the
aborted location are no longer valid since the data may be partially erased or written. A delay (tPHWL) is
required after #RESET goes to logic-high (VIH) before another command can be written.
As with any automated device, it is important to assert #RESET during system reset. When the
system comes out of reset, it expects to read from the flash memory. Automated flash memories
provide status information when accessed during block erase, full chip erase, word/byte write or lock-
bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization
may not occur because the flash memory may be providing status information instead of array data.
Winbond’s flash memories allow proper CPU initialization following a system reset through the use of
the #RESET input. In this application, #RESET is controlled by the same #RESET signal that resets
the system CPU.
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