- 您现在的位置：买卖IC网 > PDF目录300103 > W28J800BT90L (WINBOND ELECTRONICS CORP) 512K X 16 FLASH 2.7V PROM, 90 ns, PDSO48 PDF资料下载
参数资料
| 型号： | W28J800BT90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 512K X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封装： | 12 X 20 MM, TSOP-48 |
| 文件页数： | 9/49页 |
| 文件大小： | 1527K |
| 代理商： | W28J800BT90L |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页
W28J800B/T
Publication Release Date: April 11, 2003
- 17 -
Revision A4
block during full chip erase operation, WSM stops erasing. Full chip erase operation start from lower
address block, finish the higher address block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VDD = 2.7V to
3.6V and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against
erasure. If full chip erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful
full chip erase requires for boot blocks that #WP is VIH and the corresponding block lock-bit be
cleared. In parameter and main blocks case, it must clear the corresponding block lock-bit. If all blocks
are locked, SR.1 and SR.5 will be set to "1".
Word/Byte Write Command
Word/Byte write is executed by a two-cycle command sequence. Word/Byte write setup (standard
40H or alternate 10H) is written, followed by a second write that specifies the address and data
(latched on the rising edge of #WE). The WSM then takes over, controlling the word/byte write and
write verify algorithms internally. After the word/byte write sequence is written, the device
automatically outputs status register data when read (see Figure 8). The CPU can detect the
completion of the word/byte write event by analyzing the RY/#BY pin or status register bit SR.7.
When word/byte write is complete, status register bit SR.4 should be checked. If a word/byte write
error is detected, the status register should be cleared. The internal WSM verify only detects errors for
"1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it
receives another command.
Reliable word/byte writes can only occur when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the absence
of this high voltage, memory contents are protected against word/byte writes. If word/byte write is
attempted while VPP
≤ VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful
word/byte write for boot blocks requires that #WP = VIH and the corresponding block lock-bit be
cleared. In parameter and main blocks case, the corresponding block lock-bit must be cleared. If
word/byte write is attempted under these conditions, SR.1 and SR.4 will be set to "1".
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data that must be read after the Block Erase Suspend
command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1"). RY/#BY will also transition to High Z. The
period tWHRZ2 defines the block erase suspend latency.
When Block Erase Suspend command writes to the CUI, if block erase is finished, the device is
placed in read array mode. Therefore, after Block Erase Suspend command writes to the CUI, Read
Status Register command (70H) has to write to CUI, and then status register bit SR.6 should be
checked to confirm that the device is in suspend mode. At this point, a Read Array command can be
written to read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued during erase suspend to program data in
other blocks. Using the Word/Byte Write Suspend command (see Word/Byte Write Suspend
Command section), a word/byte write operation can also be suspended. During a word/byte write
相关PDF资料 |
PDF描述 |
|---|---|
| W28J800BT90C | 512K X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| W29EE011-20 | 128K X 8 EEPROM 5V, 200 ns, PDIP32 |
| W39L040P-70Z | 512K X 8 FLASH 3.3V PROM, 70 ns, PQCC32 |
| W39L040T-90Z | 512K X 8 FLASH 3.3V PROM, 90 ns, PDSO32 |
| W39V040AQZ | 512K X 8 FLASH 3.3V PROM, 11 ns, PDSO32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W28NK60Z | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:N-CHANNEL 600 V - 0.155з - 27A TO-247 Zener-Protected SuperMESH MOSFET |
| W28-SQ11A-10 | 功能描述:CIRCUIT BREAK 10A W/SWITCH RoHS:否 类别:过电压，电流，温度装置 >> 断路器 系列:W28 标准包装:3 系列:AS168X 断路器类型:热磁动式 电压:65VDC，277/480VAC 电流 - 跳闸(It):30A 极数:3 触动器类型:按片 安装类型:DIN 轨道 其它名称:4420.02104420.0210-ND486-2338AS168X-CB3G300-NDCBE AS168X-CB3G300 |
| W28-SQ11A-15 | 制造商:TE Connectivity 功能描述: |
| W28-SQ11A-3 | 制造商:TE Connectivity 功能描述:Circuit Breaker Thermal 1Pole 3A 250VAC/32VDC |
| W28-SQ11A-5 | 制造商:TE Connectivity 功能描述:Circuit Breaker Thermal 1Pole 5A 250VAC/32VDC |
发布紧急采购，3分钟左右您将得到回复。