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参数资料
| 型号： | W28J800BT90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 512K X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封装： | 12 X 20 MM, TSOP-48 |
| 文件页数： | 47/49页 |
| 文件大小： | 1527K |
| 代理商： | W28J800BT90L |
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W28J800B/T
Publication Release Date: April 11, 2003
- 7 -
Revision A4
6. PIN DESCRIPTION
SYM.
TYPE
NAME AND FUNCTION
A-1
A0
A18
INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A -1: Lower address input while #BYTE is VIL. A-1 pin changes DQ15 pin while #BYTE is VIH.
A15
A18: Main Block Address.
A12
A18: Boot and Parameter Block Address.
DQ0
DQ15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle. DQ8
DQ15 pins are not used while byte mode (#BYTE =
VIL). Then, DQ15 changes A-1address input.
#CE
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers.
#CE-high deselects the device and reduces power consumption to standby levels.
#RESET
INPUT
RESET: Resets the device internal automation. #RESET-high enables normal operation.
When driven low, #RESET inhibits write operations which provides data protection during
power transitions. Exit from reset mode sets the device to read array mode. #RESET must
be VIL during power-up.
#OE
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
#WE
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the #WE pulse.
#WP
INPUT
WRITE PROTECT: When #WP is VIL, boot blocks cannot be written or erased. When #WP is
VIH, locked boot blocks can not be written or erased. #WP is not affected parameter and main
blocks.
#BYTE
INPUT
BYTE ENABLE: #BYTE VIL places the device in byte mode (x 8), All data is then input or
output on DQ0
7, and DQ8 15 float. #BYTE VIH places the device in word mode (×16),
and turns off the A-1 input buffer.
RY/#BY
OPEN
DRAIN
OUTPUT
READY/#BUSY: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, full chip erase, word/byte write or lock-bit
configuration).
RY/#BY-high Z indicates that the WSM is ready for new commands, block erase is
suspended, and word/byte write is inactive, word/byte write is suspended, or the device is
in reset mode.
VPP
SUPPLY
BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words/bytes or
configuring lock-bits. With VPP
≤ VPPLK, memory contents cannot be altered. Block erase,
full chip erase, word/byte write and lock-bit configuration with an invalid VPP (see DC
Characteristics) produce spurious results and should not be attempted. Applying 12V
±0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each
block. VPP may be connected to 12V
±0.3V for a total of 80 hours maximum.
VDD
SUPPLY
DEVICE POWER SUPPLY: Do not float any power pins. With VDD
≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VDD voltage (see
DC Characteristics) produce spurious results and should not be attempted.
VSS
SUPPLY GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Table 1.
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