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| 型号： | W9412G6JH-5I |
| 厂商： | Winbond Electronics |
| 文件页数： | 7/53页 |
| 文件大小： | 0K |
| 描述： | IC DDR SDRAM 128MBIT 66TSOPII |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 66-TSSOP（0.400"，10.16mm 宽） |
| 供应商设备封装： | 66-TSOP II |
| 包装： | 托盘 |
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W9412G6JH
6. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 ? A11.Column address: A0 ? A8.
Provide the row address for Bank Activate commands, and
the column address and Auto-precharge bit (A10) for
Read/Write commands, to select one location out of the
28 ? 32,
35 ? 41
A0 ? A11
Address
memory array in the respective bank. A10 is sampled during
a precharge command to determine whether the precharge
applies to one bank (A10 Low) or all banks (A10 High). If
only one bank is to be precharged, the bank is selected by
BA0, BA1. The address inputs also provide the op-code
during a Mode Register Set command. BA0 and BA1 define
which mode register is loaded during the Mode Register Set
command (MRS or EMRS).
26, 27
BA0, BA1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57, DQ0 ? DQ15 Data Input/ Output
59, 60, 62, 63, 65
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
16,51
LDQS,
UDQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
24
CS
Chip Select
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
20, 47
45, 46
RAS , CAS ,
WE
LDM, UDM
CLK ,
CLK
Command Inputs
Write Mask
Differential Clock
Inputs
Command inputs (along with CS ) define the command
being entered.
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK .
CKE controls the clock activation and deactivation. When
44
CKE
Clock Enable
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
49
V REF
Reference Voltage V REF is reference voltage for inputs.
1, 18, 33
34, 48, 66
3, 9, 15, 55, 61
6, 12, 52, 58, 64
14, 17, 19, 25,
42, 43, 50, 53
V DD
V SS
V DDQ
V SSQ
NC
Power
Ground
Power for I/O
Buffer
Ground for I/O
Buffer
No Connection
Power for logic circuit inside DDR SDRAM.
Ground for logic circuit inside DDR SDRAM.
Separated power from V DD , used for output buffer, to
improve noise.
Separated ground from V SS , used for output buffer, to
improve noise.
No connection.
Publication Release Date: Jan. 14, 2014
-7-
Revision: A04
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9412G6JH-5TR | 制造商:Winbond Electronics Corp 功能描述:128M DDR SDRAM X16 200MHZ, 65N |
| W942 | 制造商:Performance Tool 功能描述:6 Piece Hook and Pick Set 制造商:PERFORMANCE TOOLS 功能描述:6 PC HOOK AND PICK SET |
| W942508BH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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