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参数资料
| 型号： | W948D2FBJX5I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 4M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 40/60页 |
| 文件大小： | 1147K |
| 代理商： | W948D2FBJX5I |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 45 -
Revision A01-003
7.14 Clock Stop
Stopping a clock during idle periods is an effective method of reducing power consumption.
The LPDDR SDRAM supports clock stop under the following conditions:
the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access
command depends on the devices AC timing parameters and the clock frequency;
the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met;
CKE is held High
When all conditions have been met, the device is either in “idle state” or “row active state” and clock stop mode
may be entered with CK held Low and
CK held High.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next
access command may be applied. Additional clock pulses might be required depending on the system
characteristics.
The following Figure shows clock stop mode entry and exit.
Initially the device is in clock stop mode
The clock is restarted with the rising edge of T0 and a NOP on the command inputs
With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for
clock stop as soon as this access command is completed
Tn is the last clock pulse required by the access command latched with T1
The clock can be stopped after Tn
7.14.1 Clock Stop Mode Entry and Exit
Valid
NOP
CMD
NOP
Tn
T2
T1
T0
CK
CKE
Command
DQ,DQS
Timing
Condition
(High-Z)
= Don't Care
Enter Clock
Stop Mode
Valid
Command
Exit Clock
Stop
Mode
Clock
Stopped
Address
相关PDF资料 |
PDF描述 |
|---|---|
| W949D6CBHX6G | 32M X 16 DDR DRAM, 5 ns, PBGA60 |
| W949D2CBJX5I | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| W949D6CBHX6E | 32M X 16 DDR DRAM, 5 ns, PBGA60 |
| W949D2CBJX6G | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| W963B6BBN80E | 512K X 16 PSEUDO STATIC RAM, 75 ns, PBGA48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W948D2FBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ, INDUST |
| W948D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics 功能描述:LOW POWER DRAM 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W948D2FBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 166MHZ, 65NM |
| W948D2FBJX6G | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPDDR |
| W948D6FB | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPDDR |
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