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参数资料
| 型号： | W948D2FBJX5I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 4M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 5/60页 |
| 文件大小： | 1147K |
| 代理商： | W948D2FBJX5I |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 13 -
Revision A01-003
6.2.2 Mode Register Definition
A6
A5
A4
0
1
0
CAS Latency
Reserved
A2
A1
A0
0
1
0
Burst Length
Reserved
2
4
8
16
Reserved
2
3
A3
0
1
Burst Type
Sequential
Interleave
Mode Register
Address Bus
A0
A1
A2
A3
A4
A5
A6
An..A7 (see Note 1)
BA0
BA1
0
0 (see Note 2)
CAS Latency
BT
Burst Length
NOTE:
1.MSB depends on LPDDR SDRAM density.
2.Alogic 0 should be programmed to all unused / undefined address bits to future compatibility.
6.2.3. Burst Length
Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length and burst type being
programmable.
The burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst
types.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.
The block is uniquely selected by A1
An when the burst length is set to two, by A2An when the burst length is set
to 4, by A3
An when the burst length is set to 8 (where An is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both read and write bursts.
相关PDF资料 |
PDF描述 |
|---|---|
| W949D6CBHX6G | 32M X 16 DDR DRAM, 5 ns, PBGA60 |
| W949D2CBJX5I | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| W949D6CBHX6E | 32M X 16 DDR DRAM, 5 ns, PBGA60 |
| W949D2CBJX6G | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| W963B6BBN80E | 512K X 16 PSEUDO STATIC RAM, 75 ns, PBGA48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W948D2FBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ, INDUST |
| W948D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics 功能描述:LOW POWER DRAM 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W948D2FBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 166MHZ, 65NM |
| W948D2FBJX6G | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPDDR |
| W948D6FB | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPDDR |
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