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参数资料
| 型号： | W9825G2DB-6 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-90 |
| 文件页数： | 38/42页 |
| 文件大小： | 916K |
| 代理商： | W9825G2DB-6 |
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W9825G2DB
Publication Release Date: Jun. 24, 2009
- 5 -
Revision A8
5. BALL DESCRIPTIONS
BALL LOCATION PIN NAME
FUNCTION
DESCRIPTION
G8,G9,F7,F3,G1,G2,
G3,H1,H2,J3,G7,H9 A0A11
Address
Multiplexed pins for row and column address. Row
address: A0
A11. Column address: A0A8. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
J7,H8
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
A1,A2,A8,A9,B1,B9,
C2,C3,C7,C8,D2,D3,
D7,D8,E2,E8,L2,L8,
M2,M3,M7,M8,N2,N3
,N7,N8,P1,P9,R1,R2,
R8,R9
DQ0
DQ31
Data Input/
Output
Multiplexed pins for data output and input.
J8
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and
previous operation continues.
J9
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
K7
CAS
Column Address
Strobe
Referred to RAS
K8
WE
Write Enable
Referred to RAS
F2,F8,K1,K9
DQM0~3
Input/output mask
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
J1
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
J2
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power-down mode, Suspend mode, or Self
Refresh mode is entered.
A7,F9,L7,R7
VDD
Power (+3.3V)
Power for input buffers and logic circuit inside DRAM.
A3,F1,L3,R3
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
B2,B7,C9,D9,E1,L1,
M9,N9,P2,P7
VDDQ
Power (+3.3V) for
I/O buffer
Separated power from VDD, to improve DQ noise
immunity.
B8,B3,C1,D1,E9,L9,
M1,N1,P3,P8,
VSSQ
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
E3,E7,H3,H7,K2,K3 NC
No Connection
No connection. (The NC pin must connect to ground or
floating.)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9825G2JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:2M ? 4 BANKS ? 32BITS SDRAM |
| W9825G2JB-6 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip SDRAM 256M-Bit 8Mx32 3.3V 90-Pin TFBGA 制造商:Winbond Electronics Corp 功能描述:IC SDRAM 256MBIT 166MHZ 制造商:Winbond Electronics Corp 功能描述:IC SDRAM 256MBIT 166MHZ 90TFBGA |
| W9825G2JB-6I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip SDRAM 256M-Bit 8Mx32 3.3V 90-Pin TFBGA 制造商:Winbond Electronics Corp 功能描述:IC SDRAM 256MBIT 166MHZ 90TFBGA |
| W9825G2JB-75 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip SDRAM 256M-Bit 8Mx32 3.3V 90-Pin TFBGA 制造商:Winbond Electronics Corp 功能描述:IC SDRAM 256MBIT 133MHZ 90TFBGA |
| W9825G6CH-75 | 制造商:Winbond Electronics Corp 功能描述:16*16bit SDRAM |
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