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参数资料
| 型号： | W987X6CBN80 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封装： | 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54 |
| 文件页数： | 7/46页 |
| 文件大小： | 1634K |
| 代理商： | W987X6CBN80 |
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Preliminary W987X6CB
Publication Release Date: June 6, 2002
- 15 -
Revision A1
Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially. The
address inputs determine the starting column address for the burst. The initial read data becomes
available after CAS latency from the issuing of the Read command. The CAS latency must be set in
the Mode Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst
operation is terminated.
When the Read with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command cannot
be interrupted by any other commands.
Refer to the diagrams for Read operation.
Write Operation
Issuing the Write command after tRCD from the bank activate command. The address inputs determine
the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the
same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on
each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins
after burst finishes will be ignored. The burst length of the Write data (Burst Length) and Addressing
Mode must be set in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto
Precharge command cannot be interrupted by any other command for the entire burst data duration.
Precharge
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of
the clock. The Precharge Command can be used to precharge each bank separately or all banks
simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.
When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after
clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted
by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge
command is issued. In this case, the DQM signal must be asserted “high” during t WR to prevent writing
the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
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| W987X6CBG75 | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
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| W989D2CBJX6E | 16M X 32 DDR DRAM, 5.4 ns, PBGA90 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W987Y6CBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W987Z6CBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W988D2FB | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPSDR |
| W988D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 256MBIT 90VFBGA |
| W988D2FBJX6I | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPSDR |
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