Preliminary W987X6CB
Publication Release Date: June 6, 2002
- 17 -
Revision A1
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
Mode Register Set Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks
are in the idle state. The data to be set in the Mode Register is transferred using the Address pins of
A0 to A11 inputs. The combination of BS0, BS1 detains this cycle is MRS or EMRS.
Mode Register Description
The Mode Register designates the operation mode for the read or write cycle. The register is
divided into four fields; (1) Burst Length field sets the length of burst data (2) Addressing Mode
selection bit to designate the column access sequence in a Burst cycle (3) CAS Latency field sets
the access time in clock cycle (4) Single Write Mode selection bit to designate write operation in
burst or single write.
Mode Register Definition
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
Reserved
A0
A7
A0
A9
A0
Write Mode
A10
A0
A11
BS0
"0"
A0
A3
A0
Addressing Mode
A0
0
A0
Sequential
A0
1
A0
Interleave
A0
A9
Single Write Mode
A0
0
A0
Burst read and Burst write
A0
1
A0
Burst read and single write
A0
A2
A1
A0
0
A0
0
1
A0
0
1
0
A0
0
1
A0
1
0
A0
1
0
1
A0
1
0
A0
1
A0
Burst Length
A0
Sequential
A0
Interleave
1
A0
1
A0
2
A0
2
A0
4
A0
4
A0
8
A0
8
A0
Reserved
A0
Reserved
A0
Full Page
A0
CAS Latency
A0
Reserved
A0
Reserved
2
A0
3
Reserved
A0
A6
A5
A4
A0
0
A0
0
1
0
A0
0
1
A0
1
0
A0
0
1
Defines it is a
MRS cycls
Reserved
"0"
BS1
"0"