
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
91
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
D2
59
MDIX
I, ID, ST
MDIX Select Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.8 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
Table 40When AMDIX_EN is active this pin is ignored.
When AMDIX_EN is inactive, all ports are forced to the
MDI or the MDIX function regardless of segmentation.
If this pin is active (high), MDI crossover (MDIX) is
selected. If this pin is inactive, non-crossover MDI
mode is set.
This pin is shared with RMII-RxER0. An external pull-
up resistor (see applications section for value) can be
used to set MDIX active while RxER0 is three-stated
during H/W reset. If no pull-up is used, the default
MDIX state is set inactive via the internal pull-down
resistor. Do not tie this pin directly to VCCIO (vs. using
a pull-up) in non-RMII modes.
L2,
L3,
M1
85
86
87
CFG_3
CFG_2
CFG_1
I, ST, ID
Global Port Configuration Defaults 1-3.
These pins are read at startup or reset. Their value at
that time is used to set the default state of register bits
can be read and overwritten after startup / reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports
M14
173
G_FX/TP_L
I, ST, ID
Global FX/TP_L Enable Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.0 for
all ports. These register bits can be read and
This input selects whether all the ports are defaulted to
TP vs. FX mode.
Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet 3 of 4)
Ball/Pin
Designation
Symbol
Type1
Signal Description2
BGA23
PQFP
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
3. The LINKHOLD ability is available only for stepping 4 (Revision D0).