
Page 175
Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
6.0 Test Specifications
Table 61
SMII - 100BASE-TX Receive Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
RxData output delay from REFCLK
rising edge
t1
1.5
–
5
ns
Minimum CL = 5 pF
Maximum CL = 20 pF
RxData Rise/Fall Time
t2
–
1.0
–
ns
–
Receive start of /J/ to CRS asserted
t3
–
21
29
BT2
Synchronous sampling of
SMII
Receive start of /T/ to CRS de-
asserted
t4
–
25
30
BT2
Synchronous sampling of
SMII
SYNC setup to REFCLK rising edge
t5
1.5
–
ns
–
SYNC hold from REFCLK rising edge
t6
1.0
–
ns
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
Note:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Figure 40
SMII - 100BASE-TX Transmit Timing
Table 62
SMII - 100BASE-TX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
t1
1.5
–
ns
–
SYNC hold from REFCLK rising edge and
TxData hold from REFCLK rising edge
t2
1.0
–
ns
–
TxEN sampled to start of /J/
t3
–
11
18
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
Note:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TxData
TPFO
t1
t2
t3
SYNC
t1
t2
REFCLK