
Page 181
Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
6.0 Test Specifications
Table 69
SS-SMII - 100BASE-FX Receive Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
REFCLK rising edge to RxCLK rising edge
t1
–
1.5
ns
–
RxData/RxSYNC output delay from RxCLK
rising edge
t2
1.5
–5ns
Minimum CL = 5pF
Maximum CL = 40pF
RxData/RxSYNC Rise/Fall time
t3
–
1
–
ns
–
Receive start of /J/ to CRS asserted
t4
–
18
23
BT2
–
Receive start of /T/ to CRS de-asserted
t5
–
21
26
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
Note:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Figure 48
SS-SMII - 100BASE-FX Transmit Timing
Table 70
SS-SMII - 100BASE-FX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
TxSYNC setup to TxCLK rising edge and
TxData setup to TxCLK rising edge
t1
1.5
–
ns
–
TxSYNC hold from TxCLK rising edge and
TxData hold to TxCLK rising edge
t2
1.0
–
ns
–
TxData to TPFO Latency
t3
–
11
13
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
Note:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TxData
TPFO
t1
t2
t3
TxSYNC
t1
t2
TxCLK