
Page 186
Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
6.0 Test Specifications
Table 76
RMII - 100BASE-FX Transmit Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
TxData<1:0>/TxEN setup to REFCLK rising edge
t1
4
–
ns
–
TxData<1:0>/TX-EN hold from REFCLK rising
edge
t2
2
–
ns
–
TxEN sampled to TPFO out (Tx latency)
t3
–
10
12
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
Note:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Figure 55
RMII - 10BASE-T Receive Timing
Table 77
RMII - 10BASE-T Receive Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test
Conditions
RxData<1:0>, CRS_DV setup to REFCLK rising
edge3
t1
4
–
14
ns
–
RxData<1:0>, CRS_DV hold from REFCLK rising
edge3
t2
2
–
14
ns
–
TPFI in to CRS_DV asserted
t3
1.5
3
4
BT2
–
TPFI quiet to CRS_DV de-asserted
t4
12
15
16
BT2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
3. Values and conditions from RMII Specification, Rev. 1.2.
Note:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
REFCLK
RxData[1:0]
TPFI
t1
t2
t3
CRS_DV
t4