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参数资料
| 型号： | X9470V24I |
| 厂商： | Intersil |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR RF PA 24-TSSOP |
| 标准包装： | 62 |
| RF 型： | CDMA，GSM，EDGE |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
X9470
X9470 STATUS REGISTER (SR) AND CONTROL REGISTER (CR) INFORMATION
Table 2. Status Register (SR)
Byte
Addr
0F hex
SR7
SHDN
SR6
INC/DEC
SR5
0
SR4
CS
SR3
0
SR2
0
SR1
WEL
SR0
Gain
STATUS REGISTER (SR)
The Status Register is located at address 0F<hex>.
This is a register used to control the write enable
latches, and monitor status of the SHDN, INC/DEC,
and CS pin. This register is separate from the Control
Register.
SR7: SHDN: Vbias SHDN Flag. Read Only—Vola-
tile. The bit keeps status of the shutdown pin, SHDN.
When this bit is HIGH, the SHDN pin is active and the
V BIAS output is disabled. When this bit is LOW, the
SHDN pin is low and V BIAS output is enabled.
SR6: INC/DEC : R ead Only—Volatile. This bit keeps
status of the INC/DEC pin. When this bit is HIGH the
counter is in increment mode, when this bit is LOW the
counter is in decrement mode.
SR4: CS: Read Only—Volatile. This bit keeps status
on the CS pin. When this bit is HIGH, the X9470 is in
closed loop mode (Rbias adjustment enabled). When
this bit is LOW the x9470 is in open loop mode (no
Rbias adjustments).
SR2, SR3, SR5: Read only
For internal test usage, should be set to 0 during SR
writes.
Table 3. Control Registers (CR)
Byte
SR1: WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the registers dur-
ing a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is set LOW, Nonvolatile writes to the registers will
be ignored, and all writes to registers will be volatile.
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once
this write operation is completed and a STOP com-
mand is issued, nonvolatile writes will then occur for all
NOVRAM registers and control bits. Once set, the,
WEL bit remains set until either reset to 0 (by writing a
“0” to the WEL bit and zeroes to the other bits of the
Status Register) or until the part powers up again.
SR0: Gain - NOVRAM
Selects VOUT and IA gain. When SR0=0, VOUT
gain = 20x, IA gain = 50x. When SR0 = 1, VOUT
gain = 50x, and IA gain = 20x. Default setting is 0.
CONTROL REGISTERS (CR)
The control registers are organized for byte opera-
tions. Each byte has a unique byte address as shown
in Table 3 below.
Bit
Addr.
<HEX>
00 hex
01 hex
Description
DCP for Vbias
DCP for VREF
Reg
Name
Vbias
Vref
7
Vb7
X
6
Vb6
X
5
Vb5
Vr5
4
Vb4
Vr4
3
Vb3
Vr3
2
Vb2
Vr2
1
Vb1
Vr1
0
Vb0
Vr0
Memory Type
NOVRAM
NOVRAM
Note:
02H to 0EH are reserved for internal manufacturing use.
18
FN8204.0
March 8, 2005
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