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参数资料
| 型号： | X9470V24I |
| 厂商： | Intersil |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR RF PA 24-TSSOP |
| 标准包装： | 62 |
| RF 型： | CDMA，GSM，EDGE |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
X9470
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 9.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 10.
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Figure 10. Acknowledge Response From Receiver
SCL from
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
Stop
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Figure 11. Valid Data Changes on the SDA Bus
SCL
SDA
Acknowledge
20
Data Stable
Data Change
Data Stable
FN8204.0
March 8, 2005
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