参数资料
| 型号： | X98017L128-3.3-Z |
| 厂商： | Intersil |
| 文件页数： | 9/29页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO DIGITIZER TRPL 128MQFP |
| 标准包装： | 66 |
| 类型： | 视频数字转换器，3 通道 AFE |
| 应用： | LCD 电视机/监控器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 产品目录页面： | 1247 (CN2011-ZH PDF) |
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17
FN8218.3
March 8, 2006
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled
(see register 0x05[1]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The X98017 provides a complete
internal DC-restore function, including the DC restore clamp
(See Figure 7) and programmable clamp timing (registers
0x14, 0x15, 0x16, and 0x23).
When AC-coupled, the DC restore clamp is applied every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x05[5] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC Starting Pixel registers (0x14 and
0x15) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x16). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC Starting Pixel registers so all the active
video pixels are skipped).
If DC-coupled operation is desired, the input to the ADC will
be the difference between the input signal (RIN1, for
example) and that channel’s ground reference (RGBGND1 in
that example).
SOG
For component YUV signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
To minimize the loading on the green channel, the SOG
input for each of the green channels should be AC-coupled
to the X98017 through a series combination of a 10nF
capacitor and a 500
resistor. Inside the X98017, a window
comparator compares the SOG signal with an internal 4 bit
programmable threshold level reference ranging from 0mV
to 300mV below the minimum sync level. The SOG
threshold level, hysteresis, and low-pass filter is
programmed via register 0x04. If the Sync-On-Green
function is not needed, the SOGIN pin(s) may be left
unconnected.
R(GB)IN1
VCLAMP
VIN+
VIN–
DC Restore
Clamp DAC
VGA1
CLAMP
GENERATION
DC Restoration
Automatic Black Level
Compensation (ABLC) Loop
Bandwidth
Control
Offset
Control
Registers
8 bit ADC
Offset
ADC
To Output
Formatter
Fixed
Offset
Fixed
Offset
0x00
ABLC
10
8
PGA
To
ABLC
Block
Input
Bandwidth
VGA2
R(GB)GND1
R(GB)IN2
R(GB)GND2
FIGURE 7. VIDEO FLOW (INCLUDING ABLC)
X98017
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相关代理商/技术参数 |
参数描述 |
|---|---|
| X98021 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:210MHz Triple Video Digitizer with Digital PLL |
| X98021_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:210MHz Triple Video Digitizer with Digital PLL |
| X98021EVAL | 制造商:Intersil Corporation 功能描述:EVALUATION BOARD FOR X98021 - Bulk |
| X98021L128-3.3 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:210MHz Triple Video Digitizer with Digital PLL |
| X98021L128-3.3-Z | 功能描述:IC TRPL VID DIGITIZER 128MQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 标准包装:250 系列:- 类型:电平移位器 应用:LCD 电视机/监控器 安装类型:表面贴装 封装/外壳:28-WFQFN 裸露焊盘 供应商设备封装:28-WQFN（4x4）裸露焊盘 包装:带卷 (TR) 其它名称:296-32523-2TPS65198RUYT-ND |
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