参数资料
| 型号： | XC2S100-5TQ144C |
| 厂商： | Xilinx Inc |
| 文件页数： | 3/99页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V 600 CLB'S 144-TQFP |
| 标准包装： | 60 |
| 系列： | Spartan®-II |
| LAB/CLB数： | 600 |
| 逻辑元件/单元数： | 2700 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 92 |
| 门数： | 100000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
| 其它名称： | 122-1229 XC2S100-5TQ144C-ND |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
11
R
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected
functions of up to 19 inputs.
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional
local routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-II FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
The dedicated carry path can also be used to cascade
function generators for implementing wide logic functions.
BUFTs
Each Spartan-II FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. See "Dedicated
Routing," page 12. Each Spartan-II FPGA BUFT has an
independent 3-state control pin and an independent input
pin.
Block RAM
Spartan-II FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory
structures implemented in CLBs.
Block RAM memory blocks are organized in columns. All
Spartan-II devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and
consequently, a Spartan-II device eight CLBs high will
contain two memory blocks per column, and a total of four
blocks.
Each block RAM cell, as illustrated in Figure 5, is a fully
synchronous dual-ported 4096-bit RAM with independent
control signals for each port. The data widths of the two
ports can be configured independently, providing built-in
bus-width conversion.
Table 6 shows the depth and width aspect ratios for the
block RAM.
The Spartan-II FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Spartan-II routing
architecture and its place-and-route software were defined
in a single optimization process. This joint optimization
minimizes long-path delays, and consequently, yields the
best system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Table 5: Spartan-II Block RAM Amounts
Spartan-II
Device
# of Blocks
Total Block RAM
Bits
XC2S15
4
16K
XC2S30
6
24K
XC2S50
8
32K
XC2S100
10
40K
XC2S150
12
48K
XC2S200
14
56K
Figure 5: Dual-Port Block RAM
Table 6: Block RAM Port Aspect Ratios
Width
Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0>
DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0>
DATA<15:0>
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADD[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
DS001_05_060100
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| XC2S100-5TQ144I | 功能描述:IC FPGA 2.5V I-TEMP 144-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-II 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC2S100-5TQG144C | 功能描述:IC SPARTAN-II FPGA 100K 144-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-II 标准包装:60 系列:XP LAB/CLB数:- 逻辑元件/单元数:10000 RAM 位总计:221184 输入/输出数:244 门数:- 电源电压:1.71 V ~ 3.465 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:388-BBGA 供应商设备封装:388-FPBGA（23x23） 其它名称:220-1241 |
| XC2S100-5TQG144I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 100K GATES 2700 CELLS 263MHZ 2.5V 144TQFP EP - Trays 制造商:Xilinx 功能描述:XLXXC2S100-5TQG144I IC SYSTEM GATE |
| XC2S100-5VQ100C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S100-5VQ100I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
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