参数资料
型号: XC2S100-5TQ144C
厂商: Xilinx Inc
文件页数: 46/99页
文件大小: 0K
描述: IC FPGA 2.5V 600 CLB'S 144-TQFP
标准包装: 60
系列: Spartan®-II
LAB/CLB数: 600
逻辑元件/单元数: 2700
RAM 位总计: 40960
输入/输出数: 92
门数: 100000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
其它名称: 122-1229
XC2S100-5TQ144C-ND
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
50
R
Revision History
Date
Version
Description
09/18/00
2.0
Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.
03/05/01
2.1
Clarified guidelines for applying power to VCCINT and VCCO
09/03/03
2.2
The following changes were made:
"Serial Modes," page 20 cautions about toggling WRITE during serial configuration.
Maximum VIH values in Table 32 and Table 33 changed to 5.5V.
In "Boundary Scan," page 13, removed sentence about lack of INTEST support.
In Table 9, page 17, added note about the state of I/Os after power-on.
In "Slave Parallel Mode," page 23, explained configuration bit alignment to SelectMap
port.
06/13/08
2.8
Added note that TDI, TMS, and TCK have a default pull-up resistor. Added note on maximum
daisy chain limit. Updated Figure 15 and Figure 18 since Mode pins can be pulled up to either
2.5V or 3.3V. Updated DLL section. Recommended using property or attribute instead of
primitive to define I/O properties. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
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