参数资料
型号: XC3S50AN-4TQ144I
厂商: Xilinx Inc
文件页数: 1/123页
文件大小: 0K
描述: IC FPGA SPARTAN 3AN 144TQFP
标准包装: 60
系列: Spartan®-3AN
LAB/CLB数: 176
逻辑元件/单元数: 1584
RAM 位总计: 55296
输入/输出数: 108
门数: 50000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
DS557 April 1, 2011
Product Specification
1
Copyright 2007–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Module 1:
Introduction
Features
Architectural Overview
Configuration Overview
In-system Flash Memory Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
Module 2:
The functionality of the Spartan-3AN FPGA family is
described in the following documents:
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-
Distributed RAM
-
SRL16 Shift Registers
-
Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE Design Tools and IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User Guide
Configuration Overview
Configuration Pins and Behavior
Bitstream Sizes
Detailed Descriptions by Mode
-
Self-contained In-System Flash mode
-
Master Serial Mode using Platform Flash PROM
-
Master SPI Mode using Commodity Serial Flash
-
Master BPI Mode using Commodity Parallel Flash
-
Slave Parallel (SelectMAP) using a Processor
-
Slave Serial using a Processor
-
JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
UG333: Spartan-3AN In-System Flash User Guide
UG334: Spartan-3AN Starter Kit User Guide
Module 3:
DC Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
Switching Characteristics
I/O Timing
Configurable Logic Block (CLB) Timing
Multiplier Timing
Block RAM Timing
Digital Clock Manager (DCM) Timing
Suspend Mode Timing
Device DNA Timing
Configuration and JTAG Timing
Module 4:
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
Additional information on the Spartan-3AN family can be
1
Spartan-3AN FPGA Family Data Sheet
DS557 April 1, 2011
Product Specification
Table 1: Production Status of Spartan-3AN FPGAs
Spartan-3AN FPGA
Status
XC3S50AN
Production
XC3S200AN
Production
XC3S400AN
Production
XC3S700AN
Production
XC3S1400AN
Production
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相关代理商/技术参数
参数描述
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