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参数资料
型号： XC3S50AN-4TQ144I
厂商： Xilinx Inc
文件页数： 90/123页
文件大小： 0K
描述： IC FPGA SPARTAN 3AN 144TQFP
标准包装： 60
系列： Spartan®-3AN
LAB/CLB数： 176
逻辑元件/单元数： 1584
RAM 位总计： 55296
输入/输出数： 108
门数： 50000
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 144-LQFP
供应商设备封装： 144-TQFP（20x20）
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
www.xilinx.com
Product Specification
69
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
02/26/07
1.0
Initial release.
08/16/07
2.0
Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38
speed files. DC specifications updated with production values. Other changes throughout.
08/31/07
2.0.1
Updated for Production release of XC3S1400AN. Improved tPEP for XC3S700AN in Table 48.
09/12/07
2.0.2
Updated for Production release of XC3S700AN.
09/24/07
2.1
Updated for Production release of XC3S400AN. Updated Software Version Requirements to note that
Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited
PCIX interface support. Added note that SPI_ACCESS (In-System Flash) is not currently supported in
simulation.
12/12/07
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
SPI_ACCESS simulation is supported in ISE 10.1 software. Removed DNA_RETENTION limit of 10
years in Table 17 since number of Read cycles is the only unique limit. Updated Setup, Hold, and
Propagation Times for the IOB Input Path to show values by device in Table 23 and Table 25. Increased
SSO recommendation for SSTL18_II in Table 32. Updated Figure 17 and Table 59 to show BPI data
synchronous to CCLK rising edge. Updated links.
06/02/08
3.1
Improved VCCAUXT and VCCO2T POR minimum in Table 7 and updated VCCO POR levels in Figure 13.
Clarified power sequencing in Note 1 of Table 7, Table 8, and Figure 13. Added VIN to Recommended
Operating Conditions in Table 10 and added reference to XAPP459, “Eliminating I/O Coupling Effects
when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical ICCINTQ and
ICCAUXQ quiescent current values by 12%-58% in Table 12. Noted latest speed file v1.39 in ISE 10.1
software in Table 19. Added reference to Sample Window in Table 24. Changed Internal SPI interface
max frequency to 50 MHz and updated other Internal SPI timing parameters to match names and
values from speed file in Table 47. Restored Units column to Table 49. Updated CCLK output maximum
period in Table 51 to match minimum frequency in Table 52. Added references to User Guides.
11/19/09
3.2
Updated selected I/O standard DC characteristics. Changed typical quiescent current temperature
from ambient to junction. Removed references to older software versions. Updated column 3 header
of Table 17 and Table 18. Added table note to Table 18. Added TIOPI and TIOPID propagation times in
Table 25. Updated TIOCKHZ and TIOCKON synchronous output enable/disable times in Table 28.
Removed VREF requirements for differential HSTL and differential SSTL in Table 30. Improved
DIFF_SSTL18_II SSO limits in Table 32. Updated table note 3 in Table 39. Removed references to old
software versions from Table 47 and Table 48. Added description of spread spectrum in Spread
Spectrum section. Updated BPI configuration waveforms in Figure 17. Updated TACC equation in
Table 60.
12/02/10
4.0
Added IIK to Table 6. Updated VIN in Table 10 and added a footnote to IL in Table 11 to note potential
leakage between pins of a differential pair. Added note 6 to Table 13. Corrected CLK High and Low
Time symbol in Table 46. Corrected symbols for TSUSPEND_GTS and TSUSPEND_GWE in Table 49.
Updated link to sign up for Alerts and updated Notice of Disclaimer.
04/01/11
4.1
In Table 31, added the equivalent pairs per bank for the XC3S50AN and XC3S400AN in the FT(G)256
package and the XC3S1400AN in the FG(G)484 package.
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相关代理商/技术参数
参数描述
XC3S50AN-4TQG144C 功能描述:IC SPARTAN-3AN FPGA 50K 144TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-3AN 标准包装:60 系列:XP LAB/CLB数:- 逻辑元件/单元数:10000 RAM 位总计:221184 输入/输出数:244 门数:- 电源电压:1.71 V ~ 3.465 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:388-BBGA 供应商设备封装:388-FPBGA（23x23） 其它名称:220-1241
XC3S50AN-4TQG144CES 制造商:Xilinx 功能描述:
XC3S50AN-4TQG144I 功能描述:IC FPGA SPARTAN-3AN50K 144-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-3AN 标准包装:60 系列:XP LAB/CLB数:- 逻辑元件/单元数:10000 RAM 位总计:221184 输入/输出数:244 门数:- 电源电压:1.71 V ~ 3.465 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:388-BBGA 供应商设备封装:388-FPBGA（23x23） 其它名称:220-1241
XC3S50AN-4TQG144ICES 制造商:Xilinx 功能描述:
XC3S50AN-5FT256C 制造商:Xilinx 功能描述:SPARTAN3AN - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN-3AN 50K 256BGA 制造商:Xilinx 功能描述:IC FPGA 195 I/O 256FTBGA
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