参数资料
| 型号： | XCS40-3PQ208I |
| 厂商： | Xilinx Inc |
| 文件页数： | 2/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V I-TEMP 208-PQFP |
| 产品变化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 标准包装： | 24 |
| 系列： | Spartan® |
| LAB/CLB数： | 784 |
| 逻辑元件/单元数： | 1862 |
| RAM 位总计： | 25088 |
| 输入/输出数： | 169 |
| 门数： | 40000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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Spartan and Spartan-XL FPGA Families Data Sheet
10
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
This high value makes them unsuitable as wired-AND
pull-up resistors.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resistor
active. Alternatively, they can be individually configured with
the pull-down resistor, or as a driven output, or to be driven
by an external source. To activate the internal pull-up, attach
the PULLUP library component to the net attached to the
pad. To activate the internal pull-down, attach the PULL-
DOWN library component to the net attached to the pad.
Set/Reset
As with the CLB registers, the GSR signal can be used to
set or clear the input and output registers, depending on the
value of the INIT attribute or property. The two flip-flops can
be individually configured to set or clear on reset and after
configuration. Other than the global GSR net, no user-con-
trolled set/reset signal is available to the I/O flip-flops
(Figure 5). The choice of set or reset applies to both the ini-
tial state of the flip-flop and the response to the GSR pulse.
Independent Clocks
Separate clock signals are provided for the input (IK) and
output (OK) flip-flops. The clock can be independently
inverted for each flip-flop within the IOB, generating either
falling-edge or rising-edge triggered flip-flops. The clock
inputs for each IOB are independent.
Common Clock Enables
The input and output flip-flops in each IOB have a common
clock enable input (see EC signal in Figure 5), which
through configuration, can be activated individually for the
input or output flip-flop, or both. This clock enable operates
exactly like the EC signal on the Spartan/XL FPGA CLB. It
cannot be inverted within the IOB.
Routing Channel Description
All internal routing channels are composed of metal seg-
ments with programmable switching points and switching
matrices to implement the desired routing. A structured,
hierarchical matrix of routing channels is provided to
achieve efficient automated routing.
This section describes the routing channels available in
Spartan/XL devices. Figure 8 shows a general block dia-
gram of the CLB routing channels. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the design.
The following description of the routing channels is for infor-
mation only and is simplified with some minor details omit-
ted. For an exact interconnect description the designer
should open a design in the FPGA Editor and review the
actual connections in this tool.
The routing channels will be discussed as follows;
CLB routing channels which run along each row and
column of the CLB array.
IOB routing channels which form a ring (called a
VersaRing) around the outside of the CLB array. It
connects the I/O with the CLB routing channels.
Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
CLB Routing Channels
The routing channels around the CLB are derived from
three types of interconnects; single-length, double-length,
and longlines. At the intersection of each vertical and hori-
zontal routing channel is a signal steering matrix called a
Programmable Switch Matrix (PSM). Figure 8 shows the
basic routing channel configuration showing single-length
lines, double-length lines and longlines as well as the CLBs
and PSMs. The CLB to routing channel interface is shown
as well as how the PSMs interface at the channel intersec-
tions.
Table 7: Supported Destinations for Spartan/XL
Outputs
Destination
Spartan-XL
Outputs
Spartan
Outputs
3.3V, CMOS
5V,
TTL
5V,
CMOS
Any device,
VCC = 3.3V,
CMOS-threshold
inputs
√√
Some(1)
Any device,
VCC = 5V,
TTL-threshold inputs
√√
√
Any device,
VCC = 5V,
CMOS-threshold
inputs
Unreliable
Data
√
Notes:
1.
Only if destination device has 5V tolerant inputs.
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相关代理商/技术参数 |
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| XCS40-3PQ240C | 功能描述:IC FPGA 5V C-TEMP 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
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| XCS40-3PQ256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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