参数资料
| 型号： | XCS40-3PQ208I |
| 厂商： | Xilinx Inc |
| 文件页数： | 45/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V I-TEMP 208-PQFP |
| 产品变化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 标准包装： | 24 |
| 系列： | Spartan® |
| LAB/CLB数： | 784 |
| 逻辑元件/单元数： | 1862 |
| RAM 位总计： | 25088 |
| 输入/输出数： | 169 |
| 门数： | 40000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
.
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The CLB clock line is shared by both flip-flops.
However, the clock is individually invertible for each flip-flop
(see CK path in Figure 3). Any inverter placed on the clock
line in the design is automatically absorbed into the CLB.
Clock Enable
The clock enable line (EC) is active High. The EC line is
shared by both flip-flops in a CLB. If either one is left discon-
nected, the clock enable for that flip-flop defaults to the
active state. EC is not invertible within the CLB. The clock
enable is synchronous to the clock and must satisfy the
setup and hold timing specified for the device.
Set/Reset
The set/reset line (SR) is an asynchronous active High con-
trol of the flip-flop. SR can be configured as either set or
reset at each flip-flop. This configuration option determines
the state in which each flip-flop becomes operational after
configuration. It also determines the effect of a GSR pulse
during normal operation, and the effect of a pulse on the SR
line of the CLB. The SR line is shared by both flip-flops. If
SR is not specified for a flip-flop the set/reset for that flip-flop
defaults to the inactive state. SR is not invertible within the
CLB.
CLB Signal Flow Control
In addition to the H-LUT input control multiplexers (shown in
box "A" of Figure 2, page 4) there are signal flow control
multiplexers (shown in box "B" of Figure 2) which select the
signals which drive the flip-flop inputs and the combinatorial
CLB outputs (X and Y).
Each flip-flop input is driven from a 4:1 multiplexer which
selects among the three LUT outputs and DIN as the data
source.
Each combinatorial output is driven from a 2:1 multiplexer
which selects between two of the LUT outputs. The X output
can be driven from the F-LUT or H-LUT, the Y output from
G-LUT or H-LUT.
Control Signals
There are four signal control multiplexers on the input of the
CLB. These multiplexers allow the internal CLB control sig-
driven from any of the four general control inputs (C1-C4 in
Figure 4) into the CLB. Any of these inputs can drive any of
the four internal control signals.
Table 2: CLB Storage Element Functionality
Mode
CK
EC
SR
D
Q
Power-Up or
GSR
XXXX
SR
Flip-Flop
Operation
XX
1
X
SR
1*
0*
D
0X
0*
X
Q
Latch
Operation
(Spartan-XL)
11*
0*
X
Q
01*
0*
D
Both
X
0
0*
X
Q
Legend:
X
Don’t care
Rising edge (clock not inverted).
SR
Set or Reset value. Reset is default.
0*
Input is Low or unconnected (default
value)
1*
Input is High or unconnected (default
value)
Figure 3: CLB Flip-Flop Functional Block Diagram
Multiplexer Controlled
by Configuration Program
DQ
Q
D
GND
GSR
Vcc
CK
EC
SR
SD
RD
DS060_03_041901
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相关代理商/技术参数 |
参数描述 |
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| XCS40-3PQ240C | 功能描述:IC FPGA 5V C-TEMP 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XCS40-3PQ240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3PQ256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3PQ256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3PQ280C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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