参数资料
| 型号： | XCS40-3PQ208I |
| 厂商： | Xilinx Inc |
| 文件页数： | 27/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V I-TEMP 208-PQFP |
| 产品变化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 标准包装： | 24 |
| 系列： | Spartan® |
| LAB/CLB数： | 784 |
| 逻辑元件/单元数： | 1862 |
| RAM 位总计： | 25088 |
| 输入/输出数： | 169 |
| 门数： | 40000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
33
Product Specification
R
Product Obsolete/Under Obsolescence
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 29. The checksum consists of the 11 most signifi-
cant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison to
a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB outputs
should not be included (Readback Capture option not
used), and if RAM is present, the RAM content must be
unchanged.
Statistically, one error out of 2048 might go undetected.
Table 17: Spartan/XL Program Data
Device
XCS05
XCS10
XCS20
XCS30
XCS40
Max System
Gates
5,000
10,000
20,000
30,000
40,000
CLBs
(Row x Col.)
100
(10 x 10)
196
(14 x 14)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
IOBs
80
112
160
192
205(4)
Part Number
XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL XCS30 XCS30XL XCS40 XCS40XL
Supply Voltage
5V
3.3V5V
3.3V5V3.3V
5V3.3V5V3.3V
Bits per Frame
126
127
166
167
226
227
266
267
306
307
Frames
428
429
572
573
788
789
932
933
1,076
1,077
Program Data
53,936
54,491
94,960
95,699
178,096
179,111
247,920
249,119
329,264
330,647
PROM Size
(bits)
53,984
54,544
95,008
95,752
178,144
179,160
247,968
249,168
329,312
330,696
Express Mode
PROM Size
(bits)
-
79,072
-
128,488
-
221,056
-
298,696
-
387,856
Notes:
1.
Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits (+1 for Spartan-XL
device)
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 (+ 1 for Spartan-XL device)
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8, rounded up to the nearest byte
2.
The user can add more "1" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame,
following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits, even for extra
leading ones at the beginning of the header.
3.
Express mode adds 57 (XCS05XL, XCS10XL), or 53 (XCS20XL, XCS30XL, XCS40XL) bits per frame, + additional start-up bits.
4.
XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.
相关PDF资料 |
PDF描述 |
|---|---|
| XCS40-3PQ208C | IC FPGA 5V C-TEMP 208-PQFP |
| XCS40-3BG256C | IC FPGA 5V C-TEMP 256-PBGA |
| ASM15DRES | CONN EDGECARD 30POS .156 EYELET |
| FMC25DRYI-S93 | CONN EDGECARD 50POS .100 DIP SLD |
| ASC65DRTS-S93 | CONN EDGECARD 130PS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS40-3PQ240C | 功能描述:IC FPGA 5V C-TEMP 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XCS40-3PQ240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3PQ256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3PQ256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3PQ280C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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