参数资料
| 型号： | XR16M698IQ100-F |
| 厂商： | Exar Corporation |
| 文件页数： | 20/58页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 32B OCTAL 100QFP |
| 标准包装： | 66 |
| 特点： | * |
| 通道数： | 8 |
| FIFO's： | 32 字节 |
| 规程： | RS485 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 包装： | 托盘 |
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TABLE 10: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY
Bit
2
Bit
1
Bit
0
INTERRUPT SOURCE(S) AND CLEARING
x
0
0 None or wake-up indicator
1
0
1 RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
2
0
1
0 RXRDY Time-out: Cleared same way as RXRDY INT.
3
0
1
1 TXRDY, THR or TSR (auto RS-485 mode) empty, clears after reading ISR register.
4
1
0
0 MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clears after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR
register.
5
1
0
1 Reserved.
6
1
0 Reserved.
7
1
1 TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
Reserved in other channels.
XR16M698
27
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
3.1.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
The 698 includes a 16-bit general purpose timer/counter. Its clock source may be selected from internal crystal
oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or re-
triggerable for a periodic signal. An interrupt may be generated when the timer times out and will show up as a
Channel 0 interrupt (see Table 10). It is controlled through 4 configuration registers [TIMERCNTL, TIMER,
TIMELSB, TIMERMSB]. These registers provide start/stop and re-triggerable or one-shot operation (see
below). The time-out output of the Timer can be set to generate an interrupt for system or event
alarm.
3.1.2.1
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit-0 of the
TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Default value is zero (timer disabled) upon powerup and reset.
TIMERMSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10
Bit-9 Bit-8
TIMERLSB Register
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1 Bit-0
16-Bit Timer/Counter Programmable Registers
3.1.2.2
TIMER [7:0] Reserved
3.1.2.3
TIMERCNTL [7:0] Register
The bits 3:0 of this register are used to issue commands. The commands are self-clearing, so reading this
register does not show the last written command. Reading this register returns a value of 0x01 when there is a
Timer interrupt pending and 0x00 at all other times.
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| XR16M698IQ100TR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 32Byte FIFO 1.8V/2.5V/3.3V 100-Pin PQFP T/R 制造商:Exar Corporation 功能描述:XR16M698IQ100TR-F |
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