参数资料
| 型号： | XR16M698IQ100-F |
| 厂商： | Exar Corporation |
| 文件页数： | 39/58页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 32B OCTAL 100QFP |
| 标准包装： | 66 |
| 特点： | * |
| 通道数： | 8 |
| FIFO's： | 32 字节 |
| 规程： | RS485 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 包装： | 托盘 |
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XR16M698
44
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
REV. 1.0.0
MSR[2]: Receiver Disable
This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to
a logic 1, the receiver will operate in one of the following ways:
■ If a character is being received at the time of setting this bit, that character will be correctly received. No
more characters will be received.
■ If the receiver is idle at the time of setting this bit, one character will still be received fully. No more
characters will be received.
The receiver can be enabled and will start receiving characters by resetting this bit to a logic 0. The receiver
will operate in one of the following ways:
■ If the receiver is idle (RX pin is HIGH) at the time of setting this bit, the next character will be received
normally. It is recommended that the receiver be idle when resetting this bit to a logic 0.
■ If the receiver is not idle (RX pin is toggling) at the time of setting this bit, the RX FIFO will be filled with
unknown data.
Any data that is in the RX FIFO can be read out at any time whether the receiver is disabled or not.
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
MSR[1]: Reserved
MSR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See “Section 2.13, Auto RS-485 Half-duplex Control” on page 19
for complete details.
Logic 0 = Normal 8-bit mode
Logic 1 = Enable 9-bit or Multidrop mode
4.11
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12
Feature Control Register (FCTR) - Read/Write
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
FCTR[7:6]: Reserved
FCTR[5]: Auto RS-485 Enable
Auto RS-485 half duplex control enable/disable.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS-485 half duplex direction control. RTS# output changes its logic level from HIGH
to LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from
LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
FCTR[4]: Infrared RX Input Logic Select
Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
FCTR [3:0] - Reserved
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| XR16M698IQ100TR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 32Byte FIFO 1.8V/2.5V/3.3V 100-Pin PQFP T/R 制造商:Exar Corporation 功能描述:XR16M698IQ100TR-F |
| XR16M752 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR16M752_09 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR16M752IL-0B-EB | 功能描述:UART 接口集成电路 Supports 16M752 32L QFN, PCI Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16M752IL32 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
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