参数资料
型号: XRT75L03DIV-F
厂商: Exar Corporation
文件页数: 111/134页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 3/3
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 128-LQFP 裸露焊盘
供应商设备封装: 128-LQFP(14x20)
包装: 托盘
XRT75L03D
á
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
73
3
FL Alarm Declared
R/O
0
FL (FIFO Limit) Alarm Declared:
This READ-ONLY bit-field indicates whether or not the Jit-
ter Attenuator block (within Channel_n) is currently declar-
ing the FIFO Limit Alarm.
The Jitter Attenuator block will declare the FIFO Limit
Alarm anytime the Jitter Attenuator FIFO comes within two
bit-periods of either overflowing or under-running.
Conversely, the Jitter Attenuator block will clear the FIFO
Limit Alarm anytime the Jitter Attenuator FIFO is NO
longer within two bit-periods of either overflowing or under-
running.
Typically, this Alarm will only be declared whenever there is
a very serious problem with timing or jitter in the system.
0 - Indicates that the Jitter Attenuator block (within
Channel_n) is NOT currently declaring the FIFO Limit
Alarm condition.
1 - Indicates that the Jitter Attenuator block (within
Channel_n) is currently declaring the FIFO Limit Alarm
condition.
NOTE: This bit-field is only active if the Jitter Attenuator
(within Channel_n) has been enabled.
2
Receive LOL Con-
dition Declared
R/O
0
Receive LOL (Loss of Lock) Condition Declared:
This READ-ONLY bit-field indicates whether or not the
Receive Section (within Channel_n) is currently declaring
the LOL (Loss of Lock) condition.
The Receive Section (of Channel_n) will declare the LOL
Condition, if any one of the following conditions are met.
If the frequency of the Recovered Clock signal differs
from that of the signal provided to the E3CLK input (for
E3
applications),
the
DS3CLK
input
(for
DS3
applications)
or
the
STS-1CLK
input
(for
STS-1
applications) by 0.5% (or 5000ppm) or more.
If the frequency of the Recovered Clock signal differs
from the line-rate clock signal (for Channel_n) that has
been generated by the SFM Clock Synthesizer PLL (for
SFM Mode Operation) by 0.5% (or 5000ppm) or more.
0 - Indicates that the Receive Section of Channel_n is NOT
currently declaring the LOL Condition.
1 - Indicates that the Receive Section of Channel_n is cur-
rently declaring the LOL Condition.
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
相关PDF资料
PDF描述
XRT75L03IV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75L04DIV-F IC LIU E3/DS3/STS-1 4CH 176TQFP
XRT75L04IV-F IC LIU E3/DS3/STS-1 4CH 176LQFP
XRT75L06DIB-F IC LIU E3/DS3/STS-1 6CH 217BGA
XRT75L06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
相关代理商/技术参数
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