参数资料
型号: XRT75L03DIV-F
厂商: Exar Corporation
文件页数: 123/134页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 3/3
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 128-LQFP 裸露焊盘
供应商设备封装: 128-LQFP(14x20)
包装: 托盘
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.0
84
3
JA RESET Ch_n
R/W
0
Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure
the Jitter Attenuator (within Channel_n) to execute a
RESET operation.
Whenever the user executes a RESET operation, then all
of the following will occur.
The READ and WRITE pointers (within the Jitter
Attenuator FIFO) will be reset to their default values.
The contents of the Jitter Attenuator FIFO will be
flushed.
NOTE: The user must follow up any "0 to 1" transition with
the appropriate write operate to set this bit-field
back to "0", in order to resume normal operation
with the Jitter Attenuator.
2
JA1 Ch_n
R/W
0
Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is
used to do any of the following.
To enable or disable the Jitter Attenuator corresponding
to Channel_n.
To select the FIFO Depth for the Jitter Attenuator within
Channel_n.
The relationship between the settings of these two bit-
fields and the Enable/Disable States, and FIFO Depths is
presented below.
1
JA in Tx Path Ch_n
R/W
0
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator
(within Channel_n) to operate in either the Transmit or
Receive path, as described below.
0 - Configures the Jitter Attenuator (within Channel_n) to
operate in the Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to
operate in the Transmit Path.
0
JA0 Ch_n
R/W
0
Jitter Attenuator Configuration Select Input - Bit 0:
Please see the description for Bit 2 (JA1 Ch_n).
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
JA0
JA1
Jitter Attenuator Mode
1
Jitter Attenuator Disabled
1
0
SONET/SDH De-Sync Mode
0
1
FIFO Depth = 32 bits
0
FIFO Depth = 16 bits
相关PDF资料
PDF描述
XRT75L03IV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75L04DIV-F IC LIU E3/DS3/STS-1 4CH 176TQFP
XRT75L04IV-F IC LIU E3/DS3/STS-1 4CH 176LQFP
XRT75L06DIB-F IC LIU E3/DS3/STS-1 6CH 217BGA
XRT75L06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
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