参数资料
| 型号： | XRT75L03DIV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 129/134页 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 3/3 |
| 规程： | DS3，E3，STS-1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP 裸露焊盘 |
| 供应商设备封装： | 128-LQFP（14x20） |
| 包装： | 托盘 |
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XRT75L03D
á
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
89
9.0
THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75L03D
The XRT75L03D LIU IC is very similar to the XRT75L03 in that they are both 3-Channel DS3/E3/STS-1 LIU
devices that also contain Jitter Attenuator blocks within each of the three channels. They are also pin to pin
compatible with each other. However, the Jitter Attenuators within the XRT75L03D has some enhancements
over and above those within the XRT75L03 (non-D) device. The Jitter Attenuator blocks within the XRT75L03D
will support all of the modes and features that exist in the XRT75L03 (non-D) device and in addition they also
support a SONET/SDH De-Sync Mode not available within the XRT75L03D.
NOTE: The "D" suffix within the part number, XRT75L03D stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks in the XRT75L03D permits the user to design
a SONET/SDH PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and
Wander requirements.
For SONET Applications
s
Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications)
s
ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
For SDH Applications
s
Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
Specifically, if the user designs in the XRT75L03D
along with a SONET/SDH Mapper IC (which can be
realized as either a standard product or as a custom logic solution, in an ASIC or FPGA), then the followind can
be accomplished;
The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
The Mapper will then terminate these STS-1 or VC-3 signals and will de-map out this DS3 or E3 data from
the incoming STS-1 SPEs or VC-3s, and output this DS3 or E3 to the DS3/E3 Facility-side towards the
XRT75L03D
This DS3 or E3 signal (as it is output from these Mapper devices) will contain a large amount intrinsic jitter
and wander due to (1) the process of asynchronously mapping a DS3 or E3 signal into a SONET or SDH
signal, (2) the occurrence of Pointer Adjustments within the SONET or SDH signal (transporting these DS3
or E3 signals) as it traverses the SONET/SDH network, and (3) clock gapping.
When the XRT75L03D has been configured to operate in the "SONET/SDH De-Sync" Mode, then it will (1)
accept this jittery DS3 or E3 clock and data signal from the Mapper device (via the Transmit System-side
interface) and (2) through the Jitter Attenuator, the XRT75L03D will reduce the Jitter and Wander amplitude
within these DS3 or E3 signals such that they (when output onto the line) will comply with the above-
mentioned intrinsic jitter and wander specifications.
9.1
BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS
This section provides an in-depth discussion on the mechanisms that will cause Jitter and Wander within a
DS3 or E3 signal that is being transported across a SONET or SDH Network.
A lot of this material is
introductory, and can be skipped by the engineer that is already experienced in SONET/SDH designs. In this
case, the user should proceed directly to “Section 9.8, Designing with the XRT75L03D” on page 118, which
describes how to configure the XRT75L03D in the appropriate set of modes in order to support this application.
In the wide-area network (WAN) in North America it is often necessary to transport a DS3 signal over a long
distance (perhaps over a thousand miles) in order to support a particular service. Now rather than realizing
this transport of DS3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of
DS3 repeaters) a common thing to do is to route this DS3 signal to a piece of equipment (such as a Terminal
MUX, which in the "SONET Community" is known as a PTE or Path Terminating Equipment). This Terminal
MUX will asynchronously map the DS3 signal into a SONET signal. At this point, the SONET network will now
transport this asynchronously mapped DS3 signal from one PTE to another PTE (which is located at the other
end of the SONET network). Once this SONET signal arrives at the remote PTE, this DS3 signal will then be
extracted from the SONET signal, and will be output to some other DS3 Terminal Equipment for further
processing.
相关PDF资料 |
PDF描述 |
|---|---|
| XRT75L03IV-F | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| XRT75L04DIV-F | IC LIU E3/DS3/STS-1 4CH 176TQFP |
| XRT75L04IV-F | IC LIU E3/DS3/STS-1 4CH 176LQFP |
| XRT75L06DIB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT75L06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT75L03DIVTR | 功能描述:时钟合成器/抖动清除器 3CHNNEL E3/DS3/STS 1 SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT75L03DIVTR-F | 功能描述:接口 - 专用 RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| XRT75L03ES | 功能描述:时钟合成器/抖动清除器 3 CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT75L03IV | 功能描述:外围驱动器与原件 - PCI 3CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT75L03IV-F | 功能描述:外围驱动器与原件 - PCI 3-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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