参数资料
型号: XRT75L03DIV-F
厂商: Exar Corporation
文件页数: 52/134页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 3/3
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 128-LQFP 裸露焊盘
供应商设备封装: 128-LQFP(14x20)
包装: 托盘
XRT75L03D
á
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
19
GENERAL CONTROL PINS
PIN #SIGNAL NAME
TYPE
DESCRIPTION
65
SR/DR
I
Single-Rail/Dual-Rail Select Input - Chip Level
This input pin is used to configure the XRT75L03D to operate in either the Sin-
gle-Rail or Dual-Rail Mode.
If the XRT75L03D is configured to operate in the Single-Rail Mode, then all of
the following will happen.
All of the B3ZS/HDB3 Encoder and Decoder blocks in the XRT75L03D will be
enabled.
The Transmit Section of each channel will accept all of the outbound data
from the System-side Equipment via the TPDATA_n (or TxDATA_n) input pin.
The Receive Section of each channel will output all of the recovered data to
the System-side Equipment via the RPOS output pin.
Each of the RNEG/LCV output pins will now function as the LCV (Line Code
Violation or Excessive Zero Event) indicator output pin.
If the user configures the device to operate in the Dual-Rail Mode, then all of the
following will happen.
All of the B3ZS/HDB3 Encoder and Decoder blocks in the XRT75L03D will be
disabled.
The Transmit Section of each channel will accept positive-polarity data via the
TPDATA_n input pin, and negative-polarity data via the TNDATA_n input pin.
The Receive Section of each channel will pulse the RPOS_n output pin "High"
for one period of RCLK_n for each time a positive-polarity pulse is received via
the RTIP_n/RRING_n input pins
Likewise, the Receive Section of each channel will also pulse the RNEG_n
output pin "High" for one period of RCLK_n for each time a negative-polarity
pulse is received via the RTIP_n/RRING_n input pins.
"Low" - Configures the XRT75L03D to operate in the Dual-Rail Mode.
"High" - Configures the XRT75L03D to operate in the Single-Rail Mode.
NOTES:
1.
This input pin is ignored and should be tied to GND if the XRT75L03D
has been configured to operate in the Host Mode.
2.
This pin is internally pulled "Low".
76
94
85
E3_0
E3_1
E3_2
I
E3 Mode Select Input - Channel 0
E3 Mode Select Input - Channel1
E3 Mode Select Input - Channel 2
This input pin, along with the corresponding STS-1/DS3_n input pin is used the
to configure a given channel within the XRT75L03D into either the DS3, E3 or
STS-1 Modes.
"High" - Configures the corresponding channel to operate in the E3 Mode.
"Low" - Configures the corresponding channel to operate in either the DS3 or
STS-1 Modes, depending upon the setting of the corresponding STS-1/DS3_n
input pin.
NOTES:
1.
This input pin is ignored and should be tied to GND if the XRT75L03D
has been configured to operate in the Host Mode.
2.
This input pin is internally pulled low.
相关PDF资料
PDF描述
XRT75L03IV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
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